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features ? maximum supply voltage 40v one programmable/adjustable boost converter two programmable buck converters one programmable linear regulator otp customer mode 16-bit serial interface two iso9141 interfaces (one interf ace programmable to lin functionality) watchdog various diagnosis functions 5 voltage sources tailored to resistor measurement charge pump small, 44-pin package esd protection against 2kv and 4kv 1. description with the introduction of the ata6264, atmel ? introduces a new generation of airbag power supplies for future airbag systems tailored to the needs of the automotive industry. it is designed in atmel?s 0.8 micron bcdmos technology. ata6264 contains all the necessary blocks to supply the microcontroller, the firing capacitors, and peripheral components of the airbag system. the power supply specifically fulfills the power requirements of dual-voltage microcontrollers used in modern ecus. the inte- grated watchdog and diagnosis blocks additionally support the safety aspects. the 8-mhz 16-bit spi enables a high communication speed. despite the high-level func- tionality, ata6264 comes in a space-saving qfp44 package. airbag power supply ic ata6264 preliminary 4929b?auto?01/07
2 4929b?auto?01/07 ata6264 [preliminary] figure 1-1. block diagram v vcore v vperi v vsat v evz cp logic vcore- regulator internal supply reference vperi- regulator evz- regulator vsat- regulator k30 gevz svsat vsat comcoi comcoo vcore svcore vperi svperi comsati comsato comevzo fbevz evz gndb ocevz gkey- logic uzp usp amux iso9141 iasg serial interface watchdog reset resq2 iasg1 iasg2 iasg4 isens gnda uzp iasg5 iasg3 k2 k1 gndd resq mosi vsat svsat v batt v batt cp_out iref vint usp sclk ssq cp k15 miso rxd2 txd1 rxd1 txd2
3 4929b?auto?01/07 ata6264 [preliminary] 1.1 block description 1.1.1 integrated boost converter evz with an external n-channel fet, the integrated boost converter evz provides 3 different volt- ages adjustable via the serial interface for the energy reserve and firing capacitors. two voltages are fixed values; one voltage can be adjusted using an external resistive divider. 1.1.2 integrated buck converter vsat the integrated buck converter vsat is a fully integrated step-down converter supplied by the boost converter, evz, and providing 7.8v, 9.1v, or 10.4v. the user can program the voltage via an otp system. 1.1.3 integrated buck converter vcore the integrated buck converter vcore is a full y integrated step-down converter supplied either by the boost converter, evz, or by the battery , and providing 1.88v, 2.5v, or 5v. the user can program the voltage via an otp system. 1.1.4 linear regulator vperi the linear regulator, vperi, is supplied from the buck converter vsat and provides an accurate voltage of 3.3v 3% or 5v 4% as a supply for sensitive elements such as sensors and adc references with the current capa bility of 100 ma. the user can program the voltage via an otp system. with a sophisticated power-sequencing concept of vcore and vperi, ata6264 sup- ports dual-voltage-supply microcontrollers, so that under all conditions the voltage difference between the two linear regulator voltages never drops below a defined value. this measure guarantees the safe operation of the system. 1.1.5 blocks included a general purpose comparator usp, for, for example, low battery voltage detection a band gap as reference for all internal voltages and currents two iso9141 interfaces, one of which is co nfigurable via otp in accordance with the lin specification five constant voltage sources with current-to-voltage mirrors used for resistance measurements, such as buckle switch detection in the range from ?0.5 ma to ?40 ma an amux block with push-pull buffer stage provides the output of all analog values such as voltage sources, low voltage detection, or the chip temperature for continuous diagnosis a 16-bit serial interface for the communication with the microcontroller which includes a 16-bit shift register, a 16-bit latch, and a decoder-logic block a watchdog to monitor the microcontroller and to generate reset signals in the case of failure internal oscillator generates internal clock signals gkey function to control the main swit ch of the ecu via a logic signal
4 4929b?auto?01/07 ata6264 [preliminary] 2. pin configuration figure 2-1. pinning qfp44 k15 evz vsat gndd vint comsati svperi vperi gnda vcore svsat usp k30 k2 iasg1 iasg2 iasg3 isens txd1 iasg5 iasg4 k1 resq rxd2 rxd1 txd2 miso ssq sclk mosi resq2 iref uzp comevzo gndb gevz ocevz fbevz cp svcore cp-out comcoo comcoi comsato 1 2 3 4 9 10 11 5 6 8 7 33 32 31 30 25 24 23 29 28 26 27 44 43 42 41 35 34 36 38 37 39 40 12 13 14 15 21 22 20 18 19 17 16 table 2-1. pin description pin symbol function 1 usp comparator input 2 k30 continuous connection to the car battery 3 k1 bus line of 1 st iso9141 interface 4 k2 bus line of 2 nd iso9141 interface 5 iasg1 output of voltage source 1 6 iasg2 output of voltage source 2 7 iasg3 output of voltage source 3 8 iasg4 output of voltage source 4 9 iasg5 output of voltage source 5 10 isens output of the current mirror from the iasgx interface 11 txd1 data input of the 1 st iso9141 interface 12 resq reset output 13 rxd2 data output of the 2 nd iso9141 interface 14 rxd1 data output of the 1 st iso9141 interface 15 txd2 data input of the 2 nd iso9141 interface 16 miso data output of the serial interface 17 ssq chip select of the serial interface 18 sclk clock input of the serial interface 19 mosi data input of the serial interface 20 resq2 redundant reset output 21 iref connection for the external reference resistor 22 uzp analog measurement output
5 4929b?auto?01/07 ata6264 [preliminary] 23 vperi input for the vperi regulator, internally used vperi supply 24 svperi output of vperi regulator power transistor 25 gnda analog gnd 26 vcore input for vcore regulator 27 comsati input of the vsat extern ally compensated error amplifier 28 vint output of internal supply voltage 29 gndd digital gnd 30 vsat input for vsat regulator, internally used vsat supply 31 svsat output of vsat regulator power transistor 32 evz input for evz regulator, internally used evz supply 33 k15 connection to car battery via the ignition key 34 comsato output of the vsat externally compensated error amplifier 35 comcoi input of the vcore externally compensated error amplifier 36 comcoo output of the vcore extern ally compensated error amplifier 37 cp-out switchable outpu t of charge pump voltage 38 svcore output of vcore regulator power transistor 39 cp charge pump output 40 fbevz input for external resistor divider to adjust evz voltage 41 ocevz input for overcurrent m easurement of the evz regulator 42 gevz gate driver output for the external fet of the evz regulator 43 gndb gnd connection of all power stages 44 comevzo output of the evz externally compensated error amplifier table 2-1. pin description pin symbol function
6 4929b?auto?01/07 ata6264 [preliminary] 3. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . all voltages are referenced to an ideal ground level of an ecu connected to the gnda, gndb and gndd pins. parameters remark minimum maximum unit voltage at pins, connected directly or indirectly to the car battery (k30, k15, usp) any combination of one or more pins applied with any voltage between the limits k30 and k15 connected via diode to v batt . usp connected via minimum 5 k ? to v batt (maximum reverse current 5 ma). ?0.3 +45 v voltage at pins, connected directly or indirectly to the car battery (k1, k2) any combination of one or more pins applied with any voltage between the limits ?25 +45 v voltage at pins, connected directly or indirectly to the car battery (iasg1, iasg2, iasg3, iasg4, iasg5) any combination of one or more pins applied with any voltage between the limits voltage necessary to drive ?40 ma stored in 20 h 45 v voltage at ecu internal pins (fbevz, evz, vsat) any combination of one or more pins applied with any voltage between the limits ?0.3 +45 v maximum rate of change at pin vsat 1v/s voltage at ecu internal pins (svsat, svcore) any combination of one or more pins applied with any voltage between the limits ?1 +45 v voltage at ecu internal pins (cp, cp-out) any combination of one or more pins applied with any voltage between the limits ?0.3 +56 v voltage at ecu internal pins (gevz, ocevz) any combination of one or more pins applied with any voltage between the limits ?0.3 +10 v voltage at ecu internal pins (comevzo, comsato, comsati, vperi, svperi, vcore, comcoi, comcoo, iref, uzp, isens, rxd1, txd1, rxd2, txd2, resq, resq2, miso, mosi, ssq, sclk, vint) these voltages can be applied in any combination with any voltage between the limits ?0.3 +7 v current at logic pins connected to voltages outside of maximum voltage ratings via resistor ?3 +3 ma esd classification at pins connected to devices outside the ecu (k30, k15) human body model (hbm) hbm aec q100-002 4000 v
7 4929b?auto?01/07 ata6264 [preliminary] esd classification at pins connected to devices outside the ecu (iasg1 to iasg5) human body model (hbm) hbm aec q100-002 3000 v esd classification at pins connected to devices outside the ecu (k1 and k2) human body model (hbm) hbm aec q100-002 2500 v general esd classification for all other pins human body model (hbm) charged device model (cdm) ? no corner pins charged device model (cdm) ? corner pins hbm aec q100-002 cdm esd stm5.3.1-1999 1500 500 750 v v v 3. absolute maximum ratings (continued) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . all voltages are referenced to an ideal ground level of an ecu connected to the gnda, gndb and gndd pins. parameters remark minimum maximum unit
8 4929b?auto?01/07 ata6264 [preliminary] 4. functional range within the functional range, the ata6264 works as specified. all voltages are referenced to the ideal ground level of an ecu connected to the gnda, gndb and gndd pins. at the beginning of each specification table, supply voltage and temperature conditions are described. table 4-1. electrical characteristics ? functional range no. parameters test conditions pi n symbol min. typ. max. unit type* 1.1 voltage on pins k30, k15, usp ?0.3 +40 v 1.1a voltage on pins k1, k2 ?25 +40 v 1.2 rate of supply voltage rise (k30, k15, k1, k2) 50 v/ s 1.3 supply voltage evz ?0.3 +40 v 1.4 supply voltage vsat ?0.3 +14 v 1.5 supply voltages vcore, vperi ?0.3 +5.5 v 1.6 supply voltage cp, cp-out ?0.3 +50 v 1.7 voltage on digital i/o pins ?0.3 +5.5 v 1.8 voltage on pins svsat, svcore ?1.0 +40 v 1.9 voltage on pins uzp, isens, comcoi, comcoo, comsato, comsati, comevzo, fbevz, iref, vint ?0.3 +5.5 v 1.10 voltage on pins gevz, ocevz ?0.3 +10 v 1.11 voltage on pin svperi ?0.3 +6 v 1.12 voltage on pins iasgx (x = 1 to 5) voltage necessary to drive ?40 ma stored in 20 h 40 v 1.14 temperatures: operating ambient temperature range operating junction temperature range storage ambient/junction temperature range ? 40 ? 40 ? 55 + 90 +150 +105 c c c 1.15 thermal resistance junction ambient 60 k/w 1.16 substrate current which can be drawn without disturbances to upper defined blocks/functions (1) ?40 ma *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. no substrate current occurs at pins k1, k2 down to v k1 , v k2 > ?25v
9 4929b?auto?01/07 ata6264 [preliminary] 4.1 protection against substrate currents due to the fact that the ata6264 is connected to the wiring harness and to components outside of the ecu, negative voltages at the following pins might occur: iasg interface: iasg1, i asg2, iasg3, iasg4, iasg5 usp comparator: usp if substrate currents occur, it is guaranteed by design that no disturbance and malfunction of the following blocks and functions will happen: no disturbance of reset block. no voltage changes of any regulators outside of their tolerances. no impact on digital circuitry (for example, changes of latches, status register, etc.) no latch up of any circuitry
10 4929b?auto?01/07 ata6264 [preliminary] 5. supply currents a minimum current has to flow into each pin for proper functioning of the ic. table 5-1. electrical characteristics ? supply currents no. parameters test conditions pi n symbol min. typ. max. unit type* 2.1 supply current at k30 standby mode: 0v = v k30 = 18v, v k15 = 3v and keylatch = off k30 i k30 050aa 2.1a supply current at k30 standby mode: 18v < v k30 = 40v, v k15 = 3v and keylatch = off k30 i k30 05maa 2.1b supply current at k30 startup mode: 0v < v k30 = 18v, v k15 > 4.15v or keylatch = on, v evz = 0v, c cp = 47 nf k30 i k30 07maa 2.1c supply current at k30 startup mode: 18v < v k30 = 40v v k15 > 4.15v or keylatch = on v evz = 0v, c cp = 47 nf k30 i k30 010maa 2.1d supply current at k30 normal mode: 0v < v k30 = 18v, v evz > v k30 , v k15 > 4v or keylatch = on, svcore open, amux measurement k30 active k30 i k30 06.5maa 2.1e supply current at k30 normal mode: 18v < v k30 = 40v, v evz > v k30 , v k15 > 4.15v or keylatch = on, svcore open, amux measurement k30 active k30 i k30 010maa 2.2 supply current at evz startup mode: 0v < v evz = 40v, v sat = v peri = v core = 0v, v k30 >5v, v k15 > 4.15v, svcore and svsat open evz i evz 05maa 2.2a supply current at evz normal mode: 0v < v evz = 40v, v peri and v core > reset threshold, v evz > v k30 , v sat = 10v, v k30 > 5v, v k15 > 4.15v, svcore and svsat open, amux measurement evz active evz i evz 06maa 2.2b supply current at evz autonomous mode: 0v < v evz = 40v, v peri and v core > reset threshold, v evz > v k30 , v sat = 10v, v k30 < 3.85v, v k15 < 3v, svcore and svsat open, amux measurement evz active evz i evz 010maa 2.3 supply current at vsat 0v < v sat = 14v, svperi open, amux measurement vsat active vsat i vsat 01.5maa 2.4 supply current at vperi 0v < v peri = 5.3v, amux measurement vperi active vperi i vperi ? 0.2 2.2 ma a 2.5 supply current at vcore 0v < v core = 5.3v, amux measurement vcore active vcore i vcore ? 0.45 1 ma a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
11 4929b?auto?01/07 ata6264 [preliminary] 5.1 discharger circuit applications using the ata6264 usually use a reverse polarity protection diode (d1 in figure 5-1 ) in the power supply to prevent any damage if the wrong polarity is applied to v k30 . unfortu- nately, this method includes some risk as can be seen in the following description: during standby mode (v k15 < 3v and keylatch = off) the ic consumes only a low current, i k30 . any peaks on the supply voltage (v pulse in figure 5-1 ) will gradually charge the blocking capacitor (c1). d1 prevents the capacitor from being discharged via the power supply and the very small quiescent current via the ic can also be neglected. this means that during long peri- ods of standby mode, the ic?s supply voltage could increase continuously until finally the maximum supply voltage limit would be exceeded and the ic could be damaged. ata6264 therefore features a discharger circuit which avoids such unwanted effects. if v k30 exceeds a threshold value of approximately 26.8v, the blocki ng capacitor is discharged via an integrated resistor until v k30 again falls below the threshold. figure 5-1. discharger circuit 5.2 initial programming of the ata6264 the ata6264 supports different output voltages at the vsat, vperi and the vcore regula- tors. in addition, different modes at the iso 9141 interfaces can be adjusted at the initial programming (ip). the memory cells are one-time programmable (otp) and cannot be changed after the ip (default values are ?0?). in general, the ip is done after mounting the ata6264 on the pcb with an in-circuit tester. the programming vo ltage of 11.7v has to be applied on pin vsat. it is also possible to use th e vsat regulator as the programmi ng voltage because vsat is pro- grammed to 11.7v (0.5v) as long as the test mode is entered and the lock bit is not set. to ensure proper programming of the ata6264, at least a 10-f electrolytic cap and a 100-nf ceramic cap have to be applied at pin vsat. v puls e v batt 26.8v k30 d1 c1 8 k ?
12 4929b?auto?01/07 ata6264 [preliminary] the following settings can be made at the initial programming: msbit lsbit vr1 vr2 vr3 vr4 ext iso/lin parity lock bit table 5-2. initial programming settings vr1 vr2 vr3 vr4 vcore vperi vsat 0 0 0 0 all regulators deactivated (default) 0 0 0 1 1.88v 3.3v 7.8v 0 0 1 0 1.88v 3.3v 9.1v 0 0 1 1 1.88v 3.3v 10.4v 0 1 0 0 2.5v 3.3v 7.8v 0 1 0 1 2.5v 3.3v 9.1v 0 1 1 0 2.5v 3.3v 10.4v 0 1 1 1 1.88v 5v 7.8v 1 0 0 0 1.88v 5v 9.1v 1 0 0 1 1.88v 5v 10.4v 1 0 1 0 2.5v 5v 7.8v 1 0 1 1 2.5v 5v 9.1v 1 1 0 0 2.5v 5v 10.4v 1 1 0 1 5v 5v 7.8v 1 1 1 0 5v 5v 9.1v 1 1 1 1 5v 5v 10.4v set to 0 set to 1 ext no external transistor at vperi (defaul t) external transistor at vperi applied set to 0 set to 1 iso/lin iso9141 mode is activated at k1 (def ault) lin mode is activated at k1
13 4929b?auto?01/07 ata6264 [preliminary] the ip data is valid only if the parity is odd. if the ip data is not valid, or if the lock bit is not set, the programming will not be executed. figure 5-2. programming sequence remove all voltages and pinloads to get out of test mode transmit ip command a9xx(h) via spi to configure ata6264 wait 1 ms wait until vsat = 11.7v transmit 5a5a(h) via spi to enable testmode set resq and txd1 to gnd and resq2 and txd2 to 5v apply 12v at k15, k30 and5v at vperi contact pins resq, resq2 txd1, txd2, ssq, mosi, sclk, vperi, k15, k30
14 4929b?auto?01/07 ata6264 [preliminary] 5.3 start-up and power-down procedure the ata6264 is powered via the pin k30 (battery voltage) and via a diode or a resistor it is con- nected to the ignition key line k15. in order to detect an interruption on one of these pins correctly, resistors are implemented at these pi ns. normally, the main supply pin of ata6264 is pin k30. in the case of a missing or a too-low voltage at pin k30, the whole ic is supplied from the backup power supply capacitor hooked up to pin evz. figure 5-3. block diagram start-up and power-down procedure vcp vcp k30 evz vevz v vsat v vperi comp vevz k15good v k15 = 3v to 4.15v (40 mv to 175mv hysteresis) serial interface (key - latch) vsat vcp comp core_en v peri = 1.25v to 1.7v (50 mv to 150 mv hysteresis) comp vsatgood v sat = 6.77v to 7.2v (200 mv to 500 mv hysteresis) comp v evz v cp k15 k30 cp gevz evzen coreswap 5v iref lost signal v k30 = 3.85v to 5v (50 mv to 150 mv hysteresis) power sequencing vsat driver svsat evz v vcor e vcore svcore vk30 ip vevz driver comp k30good vcore driver vcore driver vperi driver vperi svper ip v k30 = 6.1v to 8.1v (on) (0.5v to 1v hysteresis) comp evzgood v evz = 7.5v to 9v (on) v evz = 5.5v to 6.2v (off)
15 4929b?auto?01/07 ata6264 [preliminary] depending on the initial programming of the ata6264, the start-up procedure takes place in dif- ferent phases. 5.3.1 start-up procedure if v vcore is programmed to be 5v or 2.5v phase1: after switching on the ignition key, k15 voltage will apply at pin k15. if, in addition, the voltage at pin k30 is larger than 3.85v to 5v, the evz regulator will be enabled. the signal k15good can be replaced by the serial in terface command keylatch which can be set via the serial interface. phase2: if v evz is larger than 7.5v to 9v the vsat regulator starts oper ating and the vcore regulator will be enabled. phase3: after v vsat has reached 6.77v to 7.2v, the vperi regulator starts working. the vcore regulator starts operating depending on the charge pump voltage. 5.3.2 the power-down procedure takes place in different phases phase1: if the ignition key is switched off, k15 voltage w ill vanish at pin k15. if the serial inter- face command keylatch is not set, the evz regulator stops working. the external charge pump is still working because evz is above vsat and the vsat regulator is not in perma- nent-on mode . the charge-pump voltage still supplie s the vsat regulator and the vcore regulator. because the evz regulator stops working, vc ore will be switched to evz. phase2: the evz capacitor will be discharged, and as soon as the voltage at pin vsat drops to low, the vsat regulator will go into permanent-on mode. if vsat reaches perman ent-on mode, the external charge pump stops working and the vsat voltage falls analog to the evz voltage. if the voltage at vsat is below 6.27v to 7v, the vperi regulator will be switched off. depending on the charge-pump voltage, the vcore regulator stops working. phase3: when the voltage at the evz capacitor gets to be lower than 5.5v to 6.2v, vsat is switched off.
16 4929b?auto?01/07 ata6264 [preliminary] figure 5-4. start-up and power-down procedure if v vcore programmed to be 5v or 2.5v 5.3.3 start-up procedure if v vcore programmed to be 1.88v phase1: after switching on the igniti on key, the k15 volt age will appear at pin k15. if, in addi- tion, the voltage at pin k30 is larger than 3.85 v to 5v, the evz regulator will be enabled. the signal k15good can be replaced by the seri al interface command keylatch which can be set by the serial interface. phase2: if vevz is larger than 7.5v to 9v, the vsat re gulator starts operating. phase3: after vvsat has reached 6.77v to 7.2v, the vperi r egulator starts working. phase4: if vvperi is higher than 1.25v to 1.7v, the vcore regulator will be enabled. t v k30 3v to 4.15v 3v to 4.15v 5.5v to 6.2v too low evz voltage vsat goes into on mode charge pump deactivated 6.77v to 7.2v 7v to 6.27v 7.5v to 9v v gevz v evz v vsat v k15 v vcore v vperi t t t t t t threshold to enable vcore regulator threshold to start vcore regulator
17 4929b?auto?01/07 ata6264 [preliminary] 5.3.4 the power-down procedure for v vcore is programmed to be 1.88v phase1: if the ignition key is switched off, the k1 5 voltage will vanish at pin k15. if the serial interface command keylatch is not set, the evz regulator stops working. the external charge pump is still working because evz is above vsa t and the vsat regulator is not in the perma- nent-on mode. the charge-pum p voltage still supplies the vsat regulator and the vcore regulator. because the evz regulator stops working, vc ore will be switched to evz. phase2: the evz capacitor will be discharged, and as soon as the voltage at pin vsat drops too low, the vsat regulator will go into permanent-on mode. if vsat reaches permanent-on mode, the external charge pump stops working and the vsat voltage falls analog to the evz voltage. if the voltage at vsat is below 6.27v to 7v, the vper i regulator will be switched off. depending on the charge-pump voltage, the vcore regulator stops working. the power sequencing function for the vper i regulator is still active and guarantees a maximum voltage difference between vperi and vcore of 2.8v phase3: after vvperi becomes lower th an 1.1v to 1.55v, the vcore regulator has to stop working. phase4: when the voltage at the evz capacitor is lower than 5.5v to 6.2v, vsat is switched off. figure 5-5. start-up and power-down procedure if v vcore programmed to be 1.88v 3v to 4.15v 3v to 4.15v 5.5v to 6.2v too low evz voltage vsat goes into on mode charge pump deactivated 7.5v to 9v 7v to 6.27v 6.77v to 7.2v 1.1v to 1.55v 1.25v to 1.7v v gevz v evz v vsat v k15 v k30 v vcore v vperi t t t t t t t
18 4929b?auto?01/07 ata6264 [preliminary] 6. power supply sequencing (only active when init ial programming sets v vcore = 1.88v and v vperi = 3.3v) in order to meet the requirements of several dual-voltage-supply microcontrollers, a power-sequencing function is implemented. the ata6264 ensures that the voltage difference vperi ? vcore will not exceed 2.8v. the voltage difference between vperi and vcore is monitored. in error cases, for example, if the vcore regulator does not start to work, the difference may rise above the 2.8v threshold. in this case, the vperi regulator is switched off before reaching this level and switched on again if the voltage difference drops below a hysteresis value. figure 6-1. example for incorrect ramp up necessary for operation: v evz = 0v to 40v, v int = 3.7v to 5.47v operating conditions of all other supply pins: v k30 , v vsat , v vperi and v vcore are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . 1.88v not allowed area: v vperi - v vcore > 2.8v 3.3v v vperi v vcore t t table 6-1. electrical characteristics ? power supply sequencing no. parameters test conditions pi n symbol min typ. max. unit type* 5.1 maximum voltage difference v vperi ? v vcore vperi, vcore v vperi ? v vcore 02.8va 5.2a voltage level v vperi ? v vcore to switch off vperi regulator vperi, vcore v vperi ? v vcore 2.3 2.8 v a 5.2b hysteresis for v vperi ? v vcore to enable vperi regulator v hys 100 mv a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
19 4929b?auto?01/07 ata6264 [preliminary] figure 6-2. block diagram power supply sequencing vevz v vsat v vperi comp vevz k15good v k15 = 3v to 4.15v (40 mv to 175mv hysteresis) serial interface (key - latch) vsat vcp comp vsatgood v sat = 6.77v to 7.2v v core - regulator (200 mv to 500 mv hysteresis) comp v evz v cp k15 k30 cp gevz evzen coreswap 5v iref lost signal v k30 = 3.85v to 5v (50 mv to 150 mv hysteresis) vsat driver svsat evz v vcor e vcore svcore vk30 ip vevz driver comp k30good vperi driver delta < 2.8v vperi svper ip v k30 = 6.1v to 8.1v (on) (0.5v to 1v hysteresis) comp evzgood v evz = 7.5v to 9v (on) v evz = 5.5v to 6.2v (off)
20 4929b?auto?01/07 ata6264 [preliminary] 7. charge pump to supply the vsat and vcore dr ivers, an external charge pump is provided. both fets (1) are driven by the high charge pump voltage v cp to ensure that they can be switched to a low-ohmic state. for correct function of the charge pump, an external capacitor of c = 47 nf has to be con- nected to pin svsat, and another of c = 100 nf to pin cp. a double diode has to be implemented for proper function of the charge pump. an external series resistor is recom- mended to suppress spikes during switching of the svsat. the cp block is supplied by evz and vsat voltage and starts to operate as soon as the thresholds for vk15, k30 and evz are achieved. an additional start-up circuitry is implemented to su pport the vsat driver during the start-up phase, thus enabling a reliable system startup. the charge pump has an output cp-out to supply the external circuitry, and can be switched via the spi. it is capable of 250 a. figure 7-1. block diagram charge pump note: 1. connected to the drivers (see figure 5-3 ) svsat vsat ref ref cp i = 1.4 ma status register external circuit status register serial interface evz cp-out
21 4929b?auto?01/07 ata6264 [preliminary] necessary for operation: v evz = 5.5v to 40v or v k30 = 5.5v to 40v, v k15 > 3v, v vint = 3.7v to 5.47v operating conditions of all other supply pins: v vsat , v vperi and v vcore are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . table 7-1. electrical characte ristics ? charge pump no. parameters test conditions pi n symbol min typ. max. unit type* 6.11 supply current at pin cp cp off, supply of internal circuitry cp i cp 050aa 6.12 time between wrong cp-out voltage and valid data in status register cp-out t d 050sa 6.13 current limitation at pin cp-out cp-out i cp-out ?0.8 ?4.2 ma a 6.14 voltage difference v cp ? v evz for detecting wrong cp note: threshold is in the range of 5v to 7v cp v diff 5va 6.15 time between wrong cp voltage and valid data in status register cp t d 050sa 6.16 voltage difference v cp-out ? v evz for detecting wrong cp-out note: threshold is in the range of 5v to 7v cp-out v diff 5va 6.17 voltage at pin cp v evz = 5.5v to 40v, v k30 < v evz i cp +i cp_out = ?100 a (current consumption of v sat and v core have to be added) cp v cp v evz + 7 v evz + 11 v a 6.18 voltage at pin cp v evz = 5.5v to 40v, v k30 < v evz i cp +i cp_out = ?100 a (current consumption of v sat and v core have to be added) cp v cp v k30 + 7 v k30 + 11 v a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
22 4929b?auto?01/07 ata6264 [preliminary] 8. gkey function the gkey function is used to enab le or disable the ecu via a po werless signal. if the voltage at pin k15 is larger than 3v to 4.15v, the charge pump and the evz regulator (for correct evz function, the k30 pin has to be connected to the battery) will start operat ing. if the k15 pin is open, an internal pull-down resistor of approximately 220 k ? discharges the pin. a logical con- nection between the voltage at the k15 pin, a serial-interface-driven latch command, and the k30 voltage determines the evz enabl e signal. in order to achieve the switch function of the gkey function, a transfor mer has to be used. note: 1. less than the value shown in number 7.3 of table 8-2 on page 23 2. greater than the value shown in number 7.3 of table 8-2 on page 23 3. greater than the value shown in number 7.1 of table 8-2 on page 23 figure 8-1. application with low-current switch (gkey function used) table 8-1. overview of the start-up conditions v k30 v k15 serial-interface- driven latch (default: ?0? = of f) evz regulator low 1) x x disabled high 2) high 3) xenabled high 2) x1enabled v evz evz k30 k15 gevz comevzo fbevz evz gndb ocevz gkey- logic v batt
23 4929b?auto?01/07 ata6264 [preliminary] figure 8-2. application with hig h current switch (gkey function not used) necessary for operation: v k15 = 3v to 40v, v k30 = 3.85v to 40v operating conditions of all other supply pins: v evz , v sat , v peri and v core are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . v evz evz k30 k15 gevz comevzo fbevz evz gndb ocevz gkey- logic v batt table 8-2. electrical characteristics ? gkey function no. parameters test conditions pi n symbol min typ. max. unit type* 7.1 voltage level at k15 to enable the evz regulator v k15 increasing, v k30 > 5v k15 v k15 34.15va 7.2 hysteresis at k15 to disable the evz regulator k15 v k15 40 175 mv a 7.3 voltage level at k30 to enable the evz regulator v k30 increasing, v k15 > 4.15v k30 v k30 3.85 5 v a 7.4 hysteresis at k30 to disable the evz regulator k30 v k30 50 150 mv a 7.5 pull-down resistor at k15 k15 r k15 70 365 k ? a 7.6 pull-down resistor at k30 k30 r k30 320 1700 k ? a 7.7 current at k15 0v v k15 40v, amux measurement evz active k15 i k15 01.1maa *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
24 4929b?auto?01/07 ata6264 [preliminary] 9. evz step-up regulator a boost converter generates the supply voltage for energy reserve and firing capacitors in the system. using a voltage divider at pin fbevz, this voltage can be adjusted between 15v and 40v. thus, high-voltage charged capacitors will be used to supply the whole system during the stand-alone time (for example, broken k30 line after a crash). the step-up regulator has to start running as soon as a certain threshold voltage at the k15 pin is exceeded. the regulator has to stop running again if the voltage at the k15 pin falls below a voltage level (or voltage at pin k30 is missing, see section 5.3 ?start-up and power-down procedure? on page 14 ). an inductor is pwm-switched by an external n-channel power fet with a fixed frequency of 100 khz. a driver stage for the external fet is integrated into the ata6264. the current limita- tion of the external fet is implemented by using an external resistor in series between the source connection of the external fet and gnd, se nsing the voltage drop at this resistor via the pins ocevz and gnda. the reference section provides a reference volt age of 1.24v for the regulation loop. an error amplifier compares the reference voltage with the feedback signal, which is provided either from two different serial-interface-programmable in ternal dividers (vevz1 = 22v, vevz2 = 31.5v) or an external voltage divider network (vevzext). these dividers determine the output voltage evz. figure 9-1. evz regulator with external divider gnda - + - + low battery spi gevz l comevzo fbevz spi evz ocevz logic and driver pwm comp. error amp. bandgap reference sawtooth oscillator overcurrent evz overvoltage k30 max. duty-cycle spi r vz2 c + r vz1
25 4929b?auto?01/07 ata6264 [preliminary] figure 9-2. evz regulator with internal divider a draft formula for calculating the evz voltage , which is programmed by the external voltage divider network at pin fbevz, is: the pins evz and fbevz ha ve to be shorted in applic ations without an exte rnal divider in order to ensure a safe operation of the ata6264 in the case of an evz-pin fault. if the voltage at pin fbevz is larger th an the voltage at pin evz, the ata6264 switches the feedba ck path automat- ically to pin fbevz. the remain ing voltage at fbevz causes th e regulator to switch off. the output of the error amplifier is compared with a periodic linear ramp of a saw-tooth genera- tor by the pwm comparator. a logic signal with variable pulse width is generated, which controls the pwm frequency of the external fet. a maximu m duty cycle is determined by the duration of the falling ramp of the sa w-tooth oscillator. the saw-tooth gene rator is controlled by the internal 100-khz oscillator. gnda - + - + low battery spi gevz l comevzo fbevz spi evz ocevz logic and driver pwm comp. error amp. bandgap reference sawtooth oscillator overcurrent evz overvoltage k30 max. duty-cycle spi c + v evz v ref r vz1 r vz2 + r vz2 -------------------------------- =
26 4929b?auto?01/07 ata6264 [preliminary] figure 9-3. functional principle of the evz regulator the output transistor conduction is suppressed immediately if the current through the power fet exceeds a certain level, determined by the voltage drop across an external resistor in the range of 0.2 ? . the ata6264 itself will see a voltage at the ocevz pin. if this voltage exceeds typically 0.5v, the output transistor conduction has to be suppressed. the external fet also has to be switched off if a low battery voltage at k30 or overvoltage on pin evz is detected. multiple output pulses at pin gevz during on e oscillator perio d are suppressed by internal logic. in the default state - for example, before the minimum input voltage for starting the regulator has been reached - the external transistor is switched off. during startup, the voltage on pin evz is too low and the pwm comparator requires a duty cycle of more than 90%. due to an increasing inductance current, after several periods the overcur- rent sensor becomes active and reduces the maximum duty cycle to improve magnetic energy transfer. figure 9-4. output current during start-up a capacitance of 10 mf or more may be applied at pin evz. the equivalent series resistance (esr) should have a value of less than 0.5 ? . after power-on, the default state of the internal dividers should always be the low evz voltage divider. the voltage at pin gnda is compared with the voltage at pin gndd, and if gnda is not con- nected, bit b6 of the apace status register is set. pin gndb is also compared with pin gndd. pin gndb not being connected will also result in bit b6 being set, and, additionally, in the evz regulator being switched off. t t error amp. output = f (v evz ) sawtooth pwm output off on output current current limit t
27 4929b?auto?01/07 ata6264 [preliminary] necessary for operation: v k15 = 3v to 40v, v k30 = 5v to 40v, c gevz = 200 pf to 2 nf, v int = 3.7v to 5.47v operating conditions of all other supply pins: v sat , v peri and v core are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . table 9-1. electrical characteristics ? evz step-up regulator no. parameters test conditions pin symbol min typ. max. unit type* 8.1 switching frequency v k30 8v or v evz 8v (after startup) gevz f gevz ?5% 100 +5% khz a 8.2 switching frequency 4v < v k30 < 8v or 4v < v evz < 8v (after startup) gevz f gevz ?10% 100 +10% khz a 8.3 voltage level at k15 to start the evz regulator see number 7.1 of table 8-2 on page 23 a 8.4 hysteresis at k15 to stop the evz regulator see number 7.2 of table 8-2 on page 23 a 8.5 voltage level at k30 to start the evz regulator see number 7.3 of table 8-2 on page 23 a 8.6 hysteresis at k30 to stop the evz regulator see number 7.4 of table 8-2 on page 23 a 8.7 voltage at pin gevz to switch through the external driver v k30 3.85v to 5v (on threshold) gevz v gevz v k30 ? 0.5v v k30 va 8.8 voltage at pin gevz to switch through the external driver v k30 7v gevz v gevz 610va 8.9 driving current at pin gevz to switch through the external driver v gevz 5v gevz i gevz ?600 ?80 ma a 8.10 gate charge delivered to the external fet v gevz = 5v gevz q gevz 10 nc d 8.11 gate charge delivered to the external fet v gevz = 10v gevz q gevz 20 nc d 8.12 pull-down resistor at pin gevz gevz r gevz 20 50 k ? a 8.13 r dson of dynamic sinking transistor at gevz gevz r gevz 28 ? a 8.15 voltage between pins ocevz and gnd to detect overcurrent ocevz v ocevz 0.475 0.525 v a 8.16 maximum switch duty cycle v k30 8v or v evz 8v (after startup) v evz 8v gevz d gevz 87.5 90 92.5 % a 8.17 maximum switch duty cycle 4v < v k30 < 8v or 4v < v evz < 8v (after startup) gevz d gevz 75 90 92.5 % a 8.18 minimum switch duty cycle gevz d gevz 0%a 8.19 overvoltage at pin evz to switch off the regulator v evzext programmed (via external divider) vevz v evz 40.5 46.2 v a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
28 4929b?auto?01/07 ata6264 [preliminary] 8.19a overvoltage at pin evz to switch off the regulator v evz1 programmed vevz v evz 25 28.5 v a 8.19b overvoltage at pin evz to switch off the regulator v evz2 programmed vevz v evz 35 39.5 v a 8.20 overvoltage switch-off time time between reaching overvoltage and reaching 90% of the value at numbers 8.7 and 8.8 of table 9-1 on page 27 gevz t offov 200 ns d 8.21 overcurrent switch-off time time between reaching overcurrent and reaching 90% of the value at numbers 8.7 and 8.8 of table 9-1 on page 27 gevz t offoc 500 ns a 8.22 switch-on delay time for the boost converter output stage gevz t don 50 250 ns a 8.23 switch-on rise time for the boost converter output stage time between 0.5v and 4.5v at gevz, c gevz =2nf gevz t ron 10 200 ns a 8.24 switch-off delay time for the boost converter output stage gevz t doff 50 150 ns a 8.25 switch-off fall ti me for the boost converter output stage time between 4.5v and 0.5v at gevz, c gevz =2nf gevz t foff 10 100 ns a 8.26 leakage current at pin ocevz ocevz i ocevz ?10 +10 a a 8.27 leakage current at pin fbevz fbevz i ocevz ?10 +10 a a 8.28 switch-on th reshold via fbevz band-gap tolerance included fbevz v fbevz 1.20 1.24 v a 8.29 switch-on th reshold via fbevz band-gap tolerance included fbevz v fbevz 1.24 1.28 v a 8.30 v evz voltage #1 set by spi v evz1 programmed, band-gap tolerance included evz v evz1 20 23 v a 8.31 v evz voltage #2 set by spi v evz2 programmed, band-gap tolerance included evz v evz2 28.6 33 v a 8.31a temperature shutdown activation t off 155 185 c b 8.31b hysteresis for reactivation of gevz t hys 525kb table 9-1. electrical characteristics (continued)? evz step-up regulator no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
29 4929b?auto?01/07 ata6264 [preliminary] error amplifier 8.32 output current at pin comevzo sinking to low comevzo i comevzo 0.4 3 ma a 8.33 output current at pin comevzo driving to high comevzo i comevzo ?1000 ?150 a a 8.34 input offset voltage ?10 +10 mv d 8.35 dc open-loop gain 70 db d 8.36 unity-gain bandwidth 2 mhz d 8.37 output voltage low on pin comevzo i comevzo = 100 a comevzo v comevzo 00.2va 8.38 output voltage high on pin comevzo i comevzo = ?100 a comevzo v comevzo vint ? 0.3v vint v a gnda/gndb disconnect 8.40 gnda lost detection v gnda ? v gndd gnda v gnda 0.2 0.4 v a 8.41 delay for gnda lost detection gnda td 10 50 s a 8.42 gndb lost detection v gndb ? v gndd gndb v gndb 0.2 0.4 v a table 9-1. electrical characteristics (continued)? evz step-up regulator no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
30 4929b?auto?01/07 ata6264 [preliminary] 10. vsat power supply a stabilized vsat supply is realized by a buck converter. an external inductance is pwm-switched with a frequency of 200 khz via an internal high-side dmos power transistor. the vsat power supply is connected to the boost converter output ( evz), and uses the stored energy of the boost converter capacitor if the vo ltage at k30 is missing. the regulator uses both current and voltage feedback. the basis for the regulation loop is a temperature-compensated band-gap refere nce voltage, which is comp ared with the internally di vided output voltage vsat. the error amplifier output is applied to the inverting input of a comparator, the current feedback is connected with the positive input. the pwm f lip-flop (which is set every 5 s by the oscillator) is reset if the current feedback reaches the error amplifier level. in order to adjust the compensa- tion of the regulation loop and therefore improve the behavior in case of load changes in continuous-mode operation, pin comsato has to be connected to comsati via a compensa- tion network. because of the fact that current -mode-controlled converters exhibit sub-harmonic oscillations when operating at duty cycles hi gher than 50%, a slope compensation (which adds an artificial ramp to the comparator) is implemented. if the regulator input voltage at pin evz is too low, the regulator switches to a duty cycle of 100% (permanent-on mode). the vsat voltage can be programmed via the serial interface to one of three different voltage values during initial programming. figure 10-1. functional principle of the vsat regulator the duration of the output transistor conduc tion depends on the vsat level and current feed- back. conduction is suppressed immediately if the current through the output transistor exceeds 850 ma typically. a logic circuit disables, in the case of short spikes, multiple-pulse operation during one oscillating per iod. if pin vsat is open (vsat loss ), an internal current source con- nected to a higher voltage than vsat acts as pull-up for this pin, to prevent the vsat voltage from rising up to evz. in order to ensure the gate voltage for the output transistor, the driver stage is supplied by the charge pump (pin cp). vsat vsat - + - + svsat evz logic and driver slope compensation comp. osc error amp. bandgap reference overvoltage overcurrent q r s current measurement and leading edge blanking spi otp + comsati comsato cp
31 4929b?auto?01/07 ata6264 [preliminary] necessary for operation: v evz = 5.5v to 40v, v cp > v evz + 7v, v int = 3.7v to 5.45v operating conditions of all other supply pins: v k30 , v peri and v core are within functional range limits, t j = ?40c to +150c other pins: as defined in section 4. ?functional range? on page 8 . table 10-1. electrical characteri stics ? vsat power supply no. parameters test conditions pin symbol min typ. max. unit type* 9.1 v evz voltage for the buck converter to start running evz v evz 7.5 9 v a 9.2 v evz voltage for the buck converter to stop evz v evz 5.5 6.2 v a 9.3 regulator switch-on time via pin evz svsat t svsat 020sa 9.4 regulator switch-off time via pin evz svsat t svsat 05sa 9.5 regulator switching frequency v evz 8v svsat f svsat ?5% 200 +5% khz a 9.5a regulator switching frequency 5.5v > v evz 8v svsat f svsat ?10% 200 +10% khz a 9.6 output current limit svsat i svsat 0.8 1 a a 9.7 r dson of output transistor svsat r svsat 1 ? a 9.8 output voltage #1 only at v peri =3.3v band-gap tolerance included vsat v vsat1 ?4% 7.8 +4% v a 9.9 output voltage #2 v vsat2 programmed, band-gap tolerance included vsat v vsat2 ?4% 9.1 +4% v a 9.10 output voltage #3 v vsat3 programmed, band-gap tolerance included vsat v vsat3 ?4% 10.4 +4% v a 9.11 output transistor switch-on time time between reaching 0.1 (v evzmax ? v svsatmin ) and 0.9 (v evzmax ? v svsatmin ) 150 ns a 9.12 output transistor switch-on time time between reaching 0.9 (v evzmax ? v svsatmin ) and 0.1 (v evzmax ? v svsatmin ) 150 ns a 9.13 overvoltage switching off the regulator vsat v vsat 1.1 v satx va 9.14 overvoltage switch-on time time between reaching overvoltage and reaching 90% of v svsat maximum under on condition svsat t svsatoff 00.4sa *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. depending on implementation of slope compensation; sub-harmonics must be prevented 2. the value of the minimum load current must be higher than t he internal pull-up current at pin vsat to ensure proper func- tion of the regulator
32 4929b?auto?01/07 ata6264 [preliminary] 9.15 overcurrent switch-on time time between reaching overcurrent and reaching 90% of v svsat maximum under on condition svsat t svsatoff 00.5sa 9.16 leakage current at pin svsa t output transistor off svsat i svsat ?10 +10 a a error amplifier 9.17 maximum output current at pin comsato sinking to low comsato i comsato 200 3000 a a 9.18 maximum output current at pin comsato sourcing to high comsato i comsato ?165 ?85 a a 9.19 input impedance at pin comsati comsati r comsati 923k ? a 9.20 input offset voltage ?10 +10 mv d 9.21 dc open-loop gain 70 db d 9.22 unity-gain bandwidth 2 mhz d 9.23 output voltage low i comsato = 165 a comsato v comsato 00.3va 9.24 output voltage high i comsato = ?85 a comsato v comsato v vint ? 0.6v v vint va 9.25 leading-edge blanking time t blank 150 200 ns d 9.26 slope of artificial ramp for slope compensation dv/dt 150 (1) 240 (1) mv/s d 9.27 vsat loss detection threshold (2) i load 01.5mad table 10-1. electrical characteristics (continued)? vsat power supply no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. depending on implementation of slope compensation; sub-harmonics must be prevented 2. the value of the minimum load current must be higher than t he internal pull-up current at pin vsat to ensure proper func- tion of the regulator
33 4929b?auto?01/07 ata6264 [preliminary] 11. vperi power supply with the v peri regulator a stabilized and ripple-free voltage is gene rated out of the vsat supply voltage. this voltage is intended to be used for sensitive components, for example, sensors or reference inputs of a/d converters from microcontrollers. for this reason, a linear regulator is implemented to guarantee high ripple rejection and a precise voltage. the regulator output is short-circuit protected by an overcurrent protecti on. if pin vperi is disconnected, the regulator is switched off and resq/resq2 are set to low. figure 11-1. functional principle of the v peripheral regulator if a higher current capab ility of the regulator is re quested or if the power dissipation of the linear regulator is too high, an external transistor can boost the regulator. figure 11-2. functional principle of the vperi regula tor with external boost transistor the vperi voltage can be programmed via the serial interface to one of two different voltage values during initial programming. v peripheral v sat v peripheral linear regulator vperi svperi vsat v peripheral v sat v peripheral linear regulator vperi svperi vsat
34 4929b?auto?01/07 ata6264 [preliminary] necessary for operation: v sat > 7.5v, v int = 3.7v to 5.47v, v core < v peri + 0.3v operating conditions of all other supply pins: v k30 , v evz and v core are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . table 11-1. electrical characteristics ? vperi power supply no. parameters test conditions pin symbol min typ. max. unit type* 10.1 voltage level at vsat to enable vperi regulator vsat v vsat 6.77 7.2 v a 10.2 hysteresis at vsat to disable vperi regulator vsat v vsat 0.2 0.5 v a 10.3 output voltage #1 v vperi1 programmed, band-gap tolerance included vperi v vperi ?3.6% 5 +4% v a 10.4 output voltage #2 v vperi2 programmed, band-gap tolerance included vperi v vperi ?4% 3.3 +3% v a 10.5 output current v vsat = 7.5v to 12.5v vperi i vperi ?100 ma a 10.6 short-circuit current vperi i vperi ?200 ?110 ma a 10.7 line regulation v vsat = 8v to 12.5v i peri = ?1 ma to ?100 ma (i peri is constant during measurement) vperi v vperi ?10 +10 mv a 10.8 load regulation v sat = 8v to 12.5v (v vsat is constant during measurement) i peri = ?1 ma to ?100 ma vperi v vperi ?10 +10 mv a 10.10 supply voltage rejection i peri = ?100 ma, f = 100 khz ? 20 mhz, c peri = 47 f + 100 nf (ceramic) 40 db d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
35 4929b?auto?01/07 ata6264 [preliminary] 12. vcore power supply the voltage of the vcore regulator is generated out of the k30 voltage using a step-down reg- ulator as long as the k30 voltage is available. during times when k30 is not present (power-down or sta nd-alone time), the vcore regulator is supplied out of vevz. depending on the initial programming, the supply switch signal is derived from the coreswap comparator or the evzen comparator. the vcore voltage can be programmed via the serial interface to 3 different voltage values during initial programming. in the case of short spikes, a logic circuit dis- ables multiple-pulse opera tion during one oscillating period. the regulator uses both current and voltage feedback. in the following cases, the output transistor of the regulator is switched off at once and may be switched on again with the beginning of the next clock period: 1. if the current through the transistor exceeds the output current limit value, the transistor is switched off immediately. 2. if overvoltage is detected at the pin vcore, the transistor is switched off immediately. 3. if the feedback voltage at the pin vcore is missing (disconnected pin), the regulator is switched off. figure 12-1. functional principle of the vcore regulator in order to trim the compensation of the regulation loop and to improve the behavior at load changes, pin comcoo has to be connected to comcoi via a compensation network. because of the fact that curren t-mode-controlled converters exhibit sub-harmonic oscillations when oper- ating at duty cycles larger than 50%, a slope compensation (which adds an artificial ramp to the comparator) is implemented. if the regulator input voltage at pin evz or pin k30 is too low, the regulator switches to a duty cycle of 100% (permanent-on mode). backward feeding of evz and k30 is avoided. in order to ensure the gate voltag e for the output transistors of the regulator, the driver stages are supplied by the charge pump (pin cp). vcore vcore - + - + evz svcore k30 logic and driver slope compensation comp. osc error amp. bandgap reference overvoltage control- signal k30/evz overcurrent q r s current measurement and leading edge blanking spi otp + slope compensation current measurement and leading edge blanking comcoi comcoo cp
36 4929b?auto?01/07 ata6264 [preliminary] necessary for operation: v evz = 5.5v to 40v or v k30 = 5.5v to 40v, v cp > v evz + 7v or v cp > v k30 + 7v, v peri >v core ? 0.3v, v int = 3.7v to 5.47v operating conditions of all other supply pins: v sat is within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . table 12-1. electrical characteristics ? vcore power supply no. parameters test conditions pin symbol min typ. max. unit type* 11.1 v evz voltage for the vcore regulator to start running initial programming: v vcore = 5v or 2.5v evz v evz 7.5 9 v a 11.1a v vperi voltage for the vcore regulator to start running initial programming: v vcore = 1.88v vperi v vperi 1.25 1.7 v a 11.2 v evz voltage for the vcore regulator to stop running initial programming: v vcore = 5v or 2.5v evz v evz 5.5 6.2 v a 11.2a hysteresis at vperi for the vcore regulator to stop running initial programming: v vcore = 1.88v vperi v hys 50 150 mv a 11.3 switch-on time via pin evz svcore t svcore 020sa 11.4 switch-off time via pin evz svcore t svcore 010sa 11.5 regulator switching frequency see numbers 8.1 and 8.2 of table 9-1 on page 27 svcore f svcore a 11.6 output current limit svcore i svcore 0.7 0.9 a a 11.7 r dson of output transistor svcore r svcore 1.2 ? a 11.8 output voltage #1 v vcore1 programmed, band-gap tolerance included vcore v vcore1 ?4% 5.0 +4% v a 11.9 output voltage #2 v vcore2 programmed, band-gap tolerance included vcore v vcore2 ?4% 2.5 +4% v a 11.10 output voltage #3 v vcore3 programmed, band-gap tolerance included vcore v vcore3 ?4% 1.88 +4% v a 11.11 output transistor switch-on time time between reaching 0.1 (v k30max ? v vcoremin ) and 0.9 (v k30max ? v vcoremin ) or 0.1 (v evzmax ? v vcoremin ) and 0.9 (v evzmax ? v vcoremin ) svore t svcoreon 150 ns a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. depending on implementation of slope comp ensation, sub-harmonics have to be prevented. 2. the value of the minimum load current must be higher than the internal pull-up current at pin vcore to ensure proper function of the regulator.
37 4929b?auto?01/07 ata6264 [preliminary] 11.12 output transistor switch-off time time between reaching 0.1 (v k30max ? v vcoremin ) and 0.9 (v k30max ? v vcoremin ) or 0.1 (v evzmax ? v vcoremin ) and 0.9 (v evzmax ? v vcoremin ) svcore t svcoreoff 150 ns a 11.13 overvoltage at pin vcore for switching off the regulator and setting pin resq to low (vcore is set to 5v) see numbers 14.6 and 14.6a of table 15-2 on page 45 11.13a overvoltage at pin vcore for switching off the regulator and setting pin resq to low (vcore is set to 2.5v) see numbers 14.7 and 14.7a of table 15-2 on page 45 11.13b overvoltage at pin vcore for switching off the regulator and setting pin resq to low (vcore is set to 1.8v) see numbers 14.8 and 14.8a of table 15-2 on page 45 11.14 overvoltage switch-off time time between reaching overvoltage and reaching 90% of v score maximum under on condition svore t svcoreoff 00.4sa 11.15 overcurrent switch-off time time between reaching overcurrent and reaching 90% of v score maximum under on condition svcore t svcoreoff 00.5sa 11.16 leakage current at pin svcore output transistor off svcore i svcore ?10 10 a a error amplifier 11.17 maximum output current at pin comcoo sinking to low comcoo i comcoo 200 3000 a a 11.18 maximum output current at pin comcoo sourcing to high comcoo i comcoo ?165 ?85 a a 11.19 input impedance at pin comcoi v core = 1.88v v core = 2.5v/5v comcoi r comcoi 7.5 13 18 27 k ? k ? a 11.20 input offset voltage ?10 10 mv d 11.21 dc open loop gain 70 db d 11.22 unity-gain bandwidth 2 mhz d 11.23 output voltage low at pin comcoo i comcoo = 165 a comsato v comsato 00.3va 11.24 output voltage high at pin comcoo i comcoo = ?85 a comsato v comsato vint ? 0.6 vint v a table 12-1. electrical characteristics (c ontinued)? vcore power supply no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. depending on implementation of slope comp ensation, sub-harmonics have to be prevented. 2. the value of the minimum load current must be higher than the internal pull-up current at pin vcore to ensure proper function of the regulator.
38 4929b?auto?01/07 ata6264 [preliminary] 11.25 leading-edge blanking time t blank 150 200 ns d 11.26 slope of artificial ramp for slope compensation dv/dt 80 (1) 150 (1) mv/s d 11.27 voltage level at k30 to switch vcore supply from evz to k30 (v vcore = 1.8v or 2.5v programmed) v k30 increasing see number 7.3 of table 8-2 on page 23 a 11.28 hysteresis at k30 to switch vcore supply from k30 to evz (v vcore = 1.8v or 2.5v programmed) v k30 decreasing see number 7.4 of table 8-2 on page 23 a 11.29 voltage level at k30 to switch vcore supply from evz to k30 (v vcore = 5v programmed) v k30 increasing k30 v k30 6.1 8.1 v a 11.30 hysteresis at k30 to switch vcore supply from k30 to evz (v vcore = 5v programmed) v k30 decreasing k30 v k30 0.5 1 v a 11.31 time to switch vcore supply from evz to k30 or k30 to evz svcore t switch 07.6sd 11.32 vcore loss-detection threshold (2) vcore i load 01mad table 12-1. electrical characteristics (c ontinued)? vcore power supply no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. depending on implementation of slope comp ensation, sub-harmonics have to be prevented. 2. the value of the minimum load current must be higher than the internal pull-up current at pin vcore to ensure proper function of the regulator.
39 4929b?auto?01/07 ata6264 [preliminary] 13. usp comparator for general purpose the usp comparator is used for general purposes, for example, low battery detection. an exter- nal resistive voltage divider provides the input signal for pin usp. a missing usp connection or v usp < 2.44v sets the status register bit b7 to low. during normal operation (v usp > 2.44v) the status register bit b7 stays high. figure 13-1. functional principle of the usp comparator necessary for operation: v evz = 5.5v to 40v, v peri > reset threshold, v core > reset threshold, v int = 3.7v to 5.47v operating conditions of all other supply pins: v sat and v k30 are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . status register usp gnda to amux 2.44v - + table 13-1. electrical characteristics ? usp comparator for general purpose no. parameters test conditions pin symbol min typ. max. unit type* 12.1 input current at pin usp v usp = 2.44v usp i usp ?2.5 +2.5 a a 12.2 input current at pin usp v usp = 0 to 40v usp i usp ?2.5 +2.5 a a 12.3 threshold voltage at pin usp trigger voltage for status register bit 7= high with increasing v usp usp v usp 2.44 5% v a 12.4 de-glitching time t deglitch 20 60 s d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
40 4929b?auto?01/07 ata6264 [preliminary] 14. reference voltage and reference current generation the pin iref is an output derived directly from the chip?s internal reference voltage. this refer- ence source is a band gap. all internally used precise voltages are derived from this band-gap voltage. at pin iref a reference resistor of 12.4 k ? has to be applied, providing a reference cur- rent. all internally used precise currents are de rived from this current. in case of a missing resistor at iref, the regulators will stop. the power-sequencing bl ock still operates as specified. a defect of the band-gap reference source can be detected by a microcontroller by comparing the voltage at iref with the voltage at pin vint (internal 5v supply), because v vint is derived from a different band gap. necessary for operation: v evz = 5.5v to 40v or v k30 = 3.85v to 40v operating conditions of all other supply pins: v sat , v peri and v core are within functional range limits, t j = ?40c to +150c other pins: as defined in section 4. ?functional range? on page 8 . table 14-1. truth table for vint state k30good (v k30 >4.2v to 5v) k15good (v k15 >3vto4v) v evz v vint 1low low 0 off 2high low 0 off 3 low high 0 off 4 high high v evz < v k30 on (supply: k30) 5low lowv evz > 5.5v on (supply: evz) ? only valid if vint was already enabled via state #4 6high lowv evz > 5.5v on (supply: evz) ? only valid if vint was already enabled via state #4 7 low high v evz > 5.5v on (supply: evz) ? only valid if vint was already enabled via state #4 8 high high v evz > v k30 on (supply: k30) table 14-2. electrical characteristics ? reference voltage and reference current generation no. parameters test conditions pin symbol min typ. max. unit type* 13.1 reference voltage v iref iref v iref 1.24 4% v a 13.2 reference current iref iref i iref 100 4% a a 13.3a voltage at vint v k30 > v evz v k30 = vk30good to 5v vint v vint 3.35 5.47 v a 13.3b voltage at vint v k30 > v evz , v k30 = 5v to 6v vint v vint 3.7 5.47 v a 13.3c voltage at vint v k30 > v evz , v k30 = 6v iref v iref 4.2 5.47 v a 13.3d voltage at vint v evz > v k30 v k30 = 0v, v evz > 6v iref v iref 4.2 5.47 v a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
41 4929b?auto?01/07 ata6264 [preliminary] 15. reset function (pin resq and pin resq2) pins resq and resq2 are low-active digital out puts of the ata6264, which provide a digital ?low? signal in the case of a missing or incorrect watchdog transmission or in the case of improper vevz, vperi or vcore voltage. the voltage at pin resq depends on the proper voltages at pins evz, vcore, and vperi. the resq signal will be set to high after a 16-ms delay as soon as the vcore reset threshold and the vperi reset threshold and the evz reset threshold (signal evzgood = high) have been reached. if the watchdog circuitry does not detect a valid watchdog trigger, the resq signal is set to low again. if the watchdog was triggered successfully, resq stays high and resq2 is also set to high. in the case that an overvolta ge at vcore or vperi is detected, the voltages at pins resq and resq2 are set to low. figure 15-1. functional principle of resq, resq2 v evz v core v peri wd-logic watchdog is triggered v core is above reset threshold and below overvoltage v peri is above reset threshold and below overvoltage v evz is above reset threshold resq2 resq
42 4929b?auto?01/07 ata6264 [preliminary] figure 15-2. functional principle of resq, resq2 v evzgood spi communication re-configure prescaler while 1 st and 2nd trigger watchdog command chip internal trigger window resq2 resq 16 ms 16 ms wd cyc* wd cyc* t t t t "v core -ok" "v peri -ok" t t t any different spi cmd re-configure prescaler trg wdg cmd trg wdg cmd trg wdg cmd 4 ms 4 ms * watchdog cycle, see pages 48 and 49
43 4929b?auto?01/07 ata6264 [preliminary] the resq2 signal results from a logical and of the reset signal and an ok signal from the watchdog circuitry, so resq2 will go high after the watchdog tr iggers correctly. resq and resq2 have to be set to low if v vperi or v evz are below the specified threshold. vcore is designed as an essential supply for a microcontroller core, and therefore special supervisor circuits for this regulator will affect the sig nals at pin resq and resq2 such that both outputs are set to low if the voltage at pi n vcore spends more than 4 regulator cycles in an overvoltage or undervoltage condition at their corresponding switching marks. in addition, a detected overcurrent signal during switch-on gives information about regulator problems, and results in a low-level signal for resq/resq2. figure 15-3. functional principle of the supervisor circuit for vcore monitoring (values are valid for v vcore = 1.88v and v vperi = 3.3v) if the watchdog is triggered incorrectly, resq and resq2 are set to low as well. voltage spikes on evz smaller than or equal to 10 s to 20 s do not influence the resq or resq2 pins. if the ata6264 internal supply voltage (vint) is below its proper value, resq and resq2 are also set to low. for all voltages at vperi below the reset thre shold, pins resq an d resq2 are switched to low. both pins deliver a valid lo w until vperi goes lower than 1v. clk q d clk q d - + 3.0v to 3.16v - + high: 7.5v to 9v low: 5.5v to 6v clk q d clk q d + - 1.68v to 1.73v regulator off vcore voltage signal overcurrent vcore at regulator on on on on off off regulator on resq + - 3.44v to 3.6v vperi vcore evz clk q d clk q d clk q d clk q d - + 2.03v to 2.08v
44 4929b?auto?01/07 ata6264 [preliminary] figure 15-4. application example necessary for operation: v evz = 5.5v to 40v, v peri = 1v to 5.5v, v int = 3.7v to 5.47v operating conditions of all other supply pins: v k30 , v sat , and v core are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . table 15-1. reset truth table vperi vcore vevz watchdog resq resq2 < 1v x x x undefined (low via resistor) undefined (low via resistor) 1v to v vperi = ok x x x low low > v vperi = ok v vcore = not ok x x low low v vcore = ok evzgood = high (v evz = ok) after startup (no trigger has occurred) high low correctly triggered (trigger occurred 1 st time) high low -> high correctly triggered high high incorrectly triggered high -> low high -> low x evzgood = low (v evz = not ok) xlowlow v evz v core v peri wd-logic watchdog is triggered other peri (3.3v) safety system monitoring microcontroller (3.3v) microcontroller dual voltage supply (1.88v, 3.3v) v core is above reset "threshold" and below overvoltage v peri is above reset "threshold" and below overvoltage v evz is above reset "threshold" resq2 resq
45 4929b?auto?01/07 ata6264 [preliminary] table 15-2. electrical characteristics ? reset fu nction (pin resq and pin resq2) no. parameters test conditions pin symbol min typ. max. unit type* 14.1 resq and resq2 high level i resq, i resq2 = ?200 a to 0 a resq resq2 v resq v resq2 v vperi ? 0.8 v vperi va 14.2 resq and resq2 low level i resq, i resq2 = 0mato2ma resq resq2 v resq v resq2 00.4va 14.3 reset threshold at pin vcore v vcore is set to 5v vcore v vcore 4.5 5.03 v a 14.3a voltage difference v vcore ? reset threshold at vcore (see number 14.3) v vcore is set to 5v vcore dv vcore 0.17 0.7 v a 14.4 reset threshold at pin vcore v vcore is set to 2.5v vcore v vcore 2.25 2.5 v a 14.4a voltage difference v vcore ? reset threshold at vcore (see number 14.4) v vcore is set to 2.5v vcore dv vcore 0.1 0.35 v a 14.5 reset threshold at pin vcore v vcore is set to 1.88v vcore v vcore 1.68 1.8852 v a 14.5a voltage difference v vcore ? reset threshold at vcore (see number 14.5) v vcore is set to 1.88v vcore dv vcore 0.07 0.275 v a 14.6 overvoltage at pin v core to switch off the regulator and set resq to low v vcore is set to 5v vcore v vcore 4.97 5.5 v a 14.6a voltage difference reset threshold at vcore (see number 14.6) ? v vcore v vcore is set to 5v vcore dv vcore 0.17 0.7 v a 14.7 overvoltage at pin v core to switch off the regulator and set resq to low v vcore is set to 2.5v vcore v vcore 2.5 2.8 v a 14.7a voltage difference reset threshold at vcore (see number 14.7) ? v vcore v vcore is set to 2.5v vcore dv vcore 0.1 0.35 v a 14.8 overvoltage at pin vcore to switch off the regulator and set resq to low v vcore is set to 1.88v vcore v vcore 1.8748 2.11 v a 14.8a voltage difference reset threshold at vcore (see number 14.8) ? v vcore v vcore is set to 1.88v vcore dv vcore 0.07 0.275 v a 14.9 reset threshold at pin vperi v vperi is set to 5v vperi v vperi 4.5 4.82 v a 14.10 reset threshold at pin vperi v vperi is set to 3.3v vperi v vperi 2.94 3.16 v a 14.11 overvoltage at pin vperi to set resq to low v vperi is set to 5v vperi v vperi 5.2 5.51 v a 14.12 overvoltage at pin vperi to set resq to low v vperi is set to 3.3v vperi v vperi 3.4 3.63 v a 14.13 threshold for signal evzgood = ok v evz rising evz v evz 7.5 9 v a 14.14 threshold for signal evzgood = not ok v evz falling evz v evz 5.5 6.2 v a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
46 4929b?auto?01/07 ata6264 [preliminary] 14.15 delay time for resq and resq2 to switch to low after reaching the reset threshold of v evz resq resq2 t resq t resq2 10 20 s a 14.16 pull-down current at pin resq resq is switched to low (v resq = 0.4v), 1v v vperi <5.5v resq i resq 12maa 14.17 pull-down current at pin resq2 resq2 is switched to low (v resq = 0.4v), 1v v vperi <5.5v resq2 i resq2 12maa 14.18 pull-down resistor at pin resq, resq2 resq resq2 r resq r resq2 0.5 1.5 m ? d 14.19 output current high side resq, resq2 resq, resq2 are switched to high, v resq , v resq2 = 0v resq resq2 i resq i resq2 ?550 ?250 a a 14.20 output current low side resq, resq2 resq, resq2 are switched to high, v resq , v resq2 = v vperi resq resq2 i resq i resq2 410maa 14.21 rise time resq, resq2 30-pf external capacitive load resq resq2 t resq t resq2 4.0 s a 14.22 fall time resq, resq2 30-pf external capacitive load resq resq2 t resq t resq2 0.5 s a table 15-2. electrical characteristics (continued)? res et function (pin resq and pin resq2) no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
47 4929b?auto?01/07 ata6264 [preliminary] 16. watchdog function to verify the proper function of the microcontroller, watchdog logic is included. as the ata6264 is powered up, the resq2 signal stays low until the first valid watchdog trigger is detected. features: watchdog trigger has to be done via the serial interface in case of a watchdog-trigger mismatch, the ata6264 is set into its default state (latches, miso status, etc.) and resq is set to low. watchdog has to be triggered cyclically (prescaler for repetition time is set via serial interface command). default: 16-ms repetition time figure 16-1. watchdog trigger functional principle re-configure prescaler during 1 st and 2nd trigger watchdog command serial interface communication chip internal trigger window vcore 4.8v 5.0v 16 ms 16 ms wd cyc* wd cyc* 4 ms 4 ms resq t t t t any different spi cmd re-configure prescaler trg wdg cmd trg wdg cmd trg wdg cmd * watchdog cycle, see pages 48 and 49
48 4929b?auto?01/07 ata6264 [preliminary] requirements for successful trigger: minimum one valid different serial interface command between two trigger watchdog commands is necessary. exception: first trigger watchdog command need not be preceded by a different serial interface command. cyclic repetition for the trigger watchdog command within 25% tolerance is necessary. incorrect trigger causes resq active. the prescaler will be set to its default value with resq = low initial phase: timing for the first trigger watchdog is fixed to 16 ms after resq changes from low to high (trig- ger window 25% means 4-ms trigger window for first trigger watchdog command). after the first watchdog trigger, the prescaler can be reconfigured within a specified time window (< 1 ms). only one configuration command is allowed in this time window. for watchdog trigger handling, the serial interface reconfigure command can be chosen as a different serial interface com- mand. any further configuration in side or outside this time wi ndow will cause an immediate reset via resq. figure 16-2. reconfiguration prescaler functional principle serial interface communication chip internal trigger window no succesful reconfiguration succesful reconfiguration 1 ms 1 ms resq t t t active inactive re-configure prescaler re-configure prescaler trg wdg cmd trg wdg cmd
49 4929b?auto?01/07 ata6264 [preliminary] the trigger watchdog cycle can be set to the following retrigger times: 4 ms 8 ms 16 ms (default) 32 ms 64 ms 128 ms cyclic phase: between two trigger commands a different spi command must be seen by the spi decoder figure 16-3. watchdog trigger functional principle (successful watchdog trigger) serial interface communication chip internal trigger window t_retrigger t_retrigger t_retrigger resq t t t inactive additional spi-cmd trg wdg cmd trg wdg cmd additional spi-cmd trg wdg cmd additional spi-cmd trg wdg cmd 44 44
50 4929b?auto?01/07 ata6264 [preliminary] figure 16-4. watchdog trigger functional principle (unsuccessful watchdog trigger) serial interface communication chip internal trigger window serial interface communication chip internal trigger window t_retrigger 44 t_retrigger resq resq t t t 44 inactive inactive active active t_retrigger 44 t_retrigger t t t 44 inactive inactive active active trg wdg cmd trg wdg cmd trg wdg cmd trg wdg cmd missing command serial interface additional trg wdg cmd trg wdg cmd trg wdg cmd trg wdg cmd command serial interface additional command serial interface additional
51 4929b?auto?01/07 ata6264 [preliminary] configuration of watchdog trigger: for the configuration of the watchdog prescaler, a special serial interface command is necessary. note: a, b, and c to be set as defined in table 16-1 the status of the watchdog prescaler is indicated in the status register. description msbyte lsbyte hex code 7654321076543210 configure prescaler 0110 000011110abc 60f x table 16-1. watchdog prescaler command selection bits retrigger time (ms) abc 0 0 0 set to default (16 ms) 0014 0108 01116 10032 10164 110128 1 1 1 set to default (16 ms)
52 4929b?auto?01/07 ata6264 [preliminary] necessary for operation: v peri > reset threshold, v core > reset threshold operating conditions of all other supply pins: v k30 , v evz and v vsat are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . table 16-2. electrical characteristics ? watchdog function no. parameters test conditions pin symbol min typ. max. unit type* 15.1 oscillator frequency f os ?5% 100 +5% khz a 15.2 power-up extension of resq signal resq t resq 16 16 a 15.3 start of first watchdog trigger window after rising edge at resq t12 12 a 15.4 maximum width of first watchdog-trigger window t8 8 a 15.5 maximum time for prescaler configuration after first watchdog-trigger command t1 1 a 15.6 programmed watchdog cycle t wd as set by prescaler (default 16 ms) t wd t wd a 15.7 start of programmed watchdog window 75% t wd 75% t wd a 15.8 max. programmed window duration 50% t wd 50% t wd a 15.9 time for resq = low after watchdog timeout (missing watchdog trigger) resq t 16 16 a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 100 f os --------- - 100 f os --------- - 100 f os --------- - 100 f os --------- - 100 f os --------- -
53 4929b?auto?01/07 ata6264 [preliminary] figure 16-5. watchdog trigger re-configure prescaler during 1 st and 2nd trigger watchdog command vcc 15.2 ms 15.4 ms 15.7 ms 15.5 ms 15.3 ms 15.6 ms 15.8 ms 15.9 ms 4.75v 5.0v serial interface communication chip internal trigger window resq t t t t re-configure prescaler trg wdg cmd any different serial interface command trg wdg cmd trg wdg cmd
54 4929b?auto?01/07 ata6264 [preliminary] 17. lin/iso 9141 interfaces the ata6264 includes two complete iso 9141 interfaces. interface #1 is controlled via the pins rxd1 and txd1, interface #2 is controlled via the pins rxd2 and txd2. in order to support both iso9141 and lin bus requirements, interface #1 can be configured during initial programming. in applications where one or both iso9141 interfaces are not needed, the output transistors of k1 and k2 may be used as simple low-side transistors, switched on or off by the serial interface. in this mode, a diagnosis of the pins k1 and k2 via the analog multiplexer is possible. the k1 and k2 outputs include an internal current limitation and overtemperature protection circuit. figure 17-1. functional principle of the lin/iso 9141 interfaces necessary for operation: v evz = 9v to 40v, v k30 = 5.5v to 40v, v vperi > reset threshold, v vcore > reset threshold, v vint = 3.7v to 5.47v operating conditions of all other supply pins: v vsat is within functi onal range limits, t j = ?40c to +150c other pins: as defined in section 4. ?functional range? on page 8 . - + analog mux mode select serial interface k30 0.5 v k30 gndb uzp rxd txd c analog input k
55 4929b?auto?01/07 ata6264 [preliminary] table 17-1. electrical characteristics ? lin/iso 9141 interfaces no. parameters test conditions pin symbol min typ. max. unit type* general (valid for all modes) 16.1 pull-up current to vperi at pin txd x (x = 1, 2) txd x i txdx ?35 ?50 ?65 a a 16.2 k x input receiver low (x = 1, 2) k x v kx 0 0.4 v k30 va 16.3 k x input receiver high (x = 1, 2) k x v kx 0.6 v k30 v k30 va 16.4 k x input receiver threshold (x = 1, 2) k x v kx v k30 / 2 va 16.5 k x input receiver hysteresis (x = 1, 2) k x v kx 0.07 v k30 0.2 v k30 va 16.6 k x output sink current (x = 1, 2), k output voltage 1.5v k x i kx 35 ma a 16.7 k x output voltage drop (x = 1, 2), i kx = 0 ma to 40 ma k x v kx 1.7 v a 16.8 k x output capacitance (x = 1, 2), capacitance between kx and gndb k x c kx 10 pf d 16.9 k x output current limitation (x = 1, 2) k x i kx 50 100 ma a 16.10 k x leakage current (x = 1, 2), output driver deactivated k x i kx ?10 +10 a a 16.11 rxd x voltage drop high side (x = 1, 2), with i rxdx = 0 a to ?500 a rxd x v rxdx v vperi ? 0.8 v vperi va 16.12 rxd x voltage drop low side (x = 1, 2), i rxdx = 0 ma to 1ma rxd x v rxdx 00.4va 16.13 rxd x high-side output current (x = 1, 2), v rxdx = 0v rxd x i rxdx ?1.1 ?0.2 ma a 16.14 rxd x low-side output current (x = 1, 2), v rxdx = v vperi rxd x i rxdx 14maa 16.15 rxd x output rise time (x = 1, 2), 30-pf external load rxd x t rxdx 1s a 16.16 rxd x output fall time (x = 1, 2), 30-pf external load rxd x t rxdx 1s a 16.17 txd x input-voltage high-level threshold (v peri = 5v), (x = 1, 2) txd x v txdx 0.5 v vperi v vperi + 0.3v va 16.18 txd x input-voltage high-level threshold (v peri = 3.3v), (x = 1, 2) txd x v txdx 0.6 v peri v peri + 0.3v va 16.19 txd x input-voltage low level (v peri = 3.3v), (x = 1, 2) txd x v txdx 0.2 v vperi va 16.20 txd x input-voltage hysteresis (x = 1, 2) txd x v txdx 100 550 mv a 16.21 txd x input capacitance (x = 1, 2) txd x c txdx 5pf d 16.22 k x thermal shutdown (x = 1, 2) t jkx 155 185 c b 16.22a k x thermal-shutdown hysteresis (x=1, 2) dt jkx 525kb *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
56 4929b?auto?01/07 ata6264 [preliminary] iso 9141 mode 16.23 maximum baud rate k x f kx 62.5 kbd a 16.24 propagation delay txd x = low to k x =low (x = 1, 2), measured from txd x h to l to k x = 0.9 v k30 r kx = 510 ? to k30, c kx = 470 pf to gndb k x t pdtl 1s a 16.25 propagation delay txd x =high to kx=high (x = 1, 2), measured from txd x l to h to k x = 0.1 v k30 r kx = 510 ? to k30, c kx = 470 pf to gndb k x t pdth 1s a 16.26 k x rise time (x = 1, 2), measured from 0.1 v k30 to 0.9 v k30 r kx = 510 ? to k30, c kx = 470 pf to gndb k x t krise 3s a 16.27 k x fall time (x = 1, 2), measured from 0.9 v k30 to 0.1 v k30 r kx =510 ? to k30, c kx = 470 pf to gndb k x t kfall 3s a 16.28 propagation delay k x =low to rxd x = low (x = 1, 2), measured from k x =0.4 v k30 to rxd x =htol k x t pdkl 4s a 16.29 propagation delay k x =high to rxd x =high (x = 1, 2), from k x =0.6 v k30 to xd x = l to h k x t pdkh 4s a 16.30 symmetry of transmitter delay (x = 1, 2), t sym_tx =(t pdtl +t kfall ) ? (t pdth +t krise ) k x t sym_tx ?1 1 s a 16.31 symmetry of receiver propagation delay (x = 1, 2), t sym_rx =t pdkl ?t pdkh k x t sym_rx ?1 1 s a lin bus mode (necessary for operation: v k30 = 8v to 18v) 16.32 slew rate for rising and falling edge measured between high level = 0.8 v k30 and low level = 0.2 v k30 , r k1 =1k ? to k30, c k1 = 3.3 nf to gndb k 1 dv k1 /dt 1 3 v/s a 16.33 maximum baud rate k 1 t kx 20 kbd a 16.34 propagation delay txd 1 low to k 1 =low measured from txd 1 h-> l to k 1 = 0.9 v k30 r k1 = 1 k ? to k30, c k1 = 3.3 nf to gndb k 1 t pdtl 2.5 s a 16.35 propagation delay txd 1 high to k 1 = high measured from txd 1 l to h to k 1 = 0.1 v k30 r k1 =1k ? to k30, c k1 = 3.3 nf to gndb k 1 t pdth 2.5 s a 16.36 propagation delay k 1 low to rxd 1 = low measured from k 1 =0.4 v k30 to rxd 1 =htol k 1 t pdkl 4s a table 17-1. electrical characteristics (continued)? lin/iso 9141 interfaces no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
57 4929b?auto?01/07 ata6264 [preliminary] figure 17-2. timing lin/iso 9141 interface 16.37 propagation delay k 1 high to rxd 1 =high measured from k 1 =0.6 v k30 to rxd 1 =ltoh k 1 t pdkh 4s a 16.38 symmetry of transmitter delay t sym_t1 =t pdtl ?t pdth k 1 t sym_t1 ?1 1 s a 16.39 symmetry of receiver propagation delay t sym_r1 =t pdkl ?t pdkh k 1 t sym_r1 ?1 1 s a ls driver mode 16.40 k x output voltage drop i kx =40ma i kx =20ma k x v kx 1.7 1.2 va 16.41 k x switch-on delay (x = 1, 2), measured from rising edge of ssq to v kx = 16.40v, r kx =250 ? to k30, c kx = 3.3 nf to gndb k x t kx 50 s a 16.42 k x switch-off delay (x = 1, 2), measured from rising edge of ssq to v kx =0.9 v k30 , r kx = 250 ? to k30, c kx = 3.3 nf to gndb k x t kx 10 s a 16.43 k x leakage current (x = 1, 2), output driver deactivated, amux measurement activated and deactivated k30 = 5.5v to 15v k30 > 15v to 25v k30 > 25v to 40v k x i kx ?10 ?10 ?10 +100 +160 +260 a a a a a a 16.44 k x leakage current (x = 1, 2), output driver deactivated, amux measurement deactivated k30 = 5.5v to 40v k x = ?25v k x i kx ?150 +10 a a table 17-1. electrical characteristics (continued)? lin/iso 9141 interfaces no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 90% baudrate baudrate = t on + t off 2 60% 40% 10% t pdtl v k v txd v rxd 2 t pdkl t pdkh t pdth
58 4929b?auto?01/07 ata6264 [preliminary] 18. voltage/current sources (iasg x sources) for a variable resistance measurement and especia lly for buckle-switch detection, five constant voltage sources, switchable between two different voltages (v1 and v2) are implemented. the current delivered by these voltage sources is mirrored by a factor of 1 / 10 or 1 / 15 to the pin isens and causes a voltage drop at the external resistor connected to this pin. this voltage drop can be measured at pin uzp by choosing the corresponding amux command. the exter- nal resistor at pin iasg x can be calculated using the following formulas: or the current through pin iasg x is internally limited to a value between i iasgx = ?150 ma and ?50 ma. if the voltage at pin isens becomes higher than v vperi , the voltage at pin iasg and, consequently, the current at pin iasg x is reduced until v isens =v vperi . this function can be used to reduce the current limitation of pin iasg x to values lower than the internal limit by choos- ing an adequate external resistor at pin isens. in this case, the maximum current through pin iasg x can be calculated as: or for high accuracy, the iasgx current needs to be between 0.5 ma and 40 ma, and the maxi- mum isens voltage must be < v peri ? 40%. under a clamping condition, the voltage at pin isens is clamped to v peri + 5%. calculation of the resistor at pin isens: in applications with one or more unused iasg channels, the iasg pins can be used as mea- surement inputs. the five iasg pins are conne cted to the analog multiplexer block via different dividers. voltages applied to these iasg pins ca n be measured at the uzp pin, selected via spi commands. r iasgx r isens 10 ------------------ v v1 v v2 ? v isens1 v isens2 ? ----------------------------------------------- = r iasgx r isens 15 ------------------ v v1 v v2 ? v isens1 v isens2 ? ----------------------------------------------- = i iasgxlim 10 v vperi r isens ------------------ = i iasgxlim 15 v vperi r isens ------------------ = rsens 0.96 v peri cr1 i asgmax -------------------- =
59 4929b?auto?01/07 ata6264 [preliminary] figure 18-1. functional principle of the iasg interface necessary for operation: v vcore and v vperi > reset threshold, v evz = 9v to 40v for operation with iasgx switched to 5v v vcore and v vperi > reset threshold, v evz = 15v to 40v for operation with iasgx switched to 10v v int = 3.7v to 5.47v, v cp > v evz + 7v operating conditions of all other supply pins: v k30 and v vsat are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 , c iasgx 10 nf and 825 ? r isens 5k ? serial interface serial interface uzp current mirror serial interface analog multiplexer short circuit protection 10 15 iasgx c > 10 pf riasgx i = f(r) i/10 or i/15 isens resistive sensor current limit if v isens >v peri v v1 v v2 1 1 - + r isens
60 4929b?auto?01/07 ata6264 [preliminary] table 18-1. electrical characteristics ? voltage/current sources (iasg x sources) no. parameters test conditions pin symbol min typ. max. unit type* 17.1 output voltage (v1) (x = 1 to 5), ?40 ma < i iasgx < ?0.5 ma v isens = 0.96 v vperi iasg x v1 iasgx ?6% 10 +6% v a 17.2 output voltage (v2) (x = 1 to 5), ?40 ma < i iasgx < ?0.5 ma v isens = 0.96 v vperi iasg x switched to 5v v evz > 11v iasg x v2 iasgx ?6% 5 +6% v a 17.2a output voltage (v2) (x = 1 to 5), ?25 ma < i iasgx < ?0.5 ma v isens = 0.96 v vperi iasg x switched to 5v v evz > 9v to 11v iasg x v2 iasgx ?6% 5 +6% v a 17.3 output voltage overshoot at iasgx due to regulator characteristic (x = 1 to 5) when iasg = 5v when iasg = 10v iasg x ? v iasgx 5.9 11.3 v v a a 17.4 maximum duration of voltage overshoot at iasgx (x = 1 to 5), with v iasgx = 10v / 0.5 ma < r load < v iasgx = 5v / 40 ma iasg x t iasgx 30 s a 17.5 linear range for current mirror at iasgx (x = 1 to 5), 0v = v isens = 0.96 v peri iasg x i iasgx ?40 ?0.5 ma a 17.6 internal current limitation at iasg x (x = 1 to 5) iasg x i iasgx ?150 ?50 ma a 17.7 current ratio #1 (x = 1 to 5), cr 1x = i iasgx / i isens 0v = v isens = 0.96 v vperi ?40 ma < i iasgx < ?0.5ma iasg x cr 1x ?3% 9.9 +3% a 17.8 current ratio #2 (x = 1 to 5), cr 2x = i iasgx /i isens 0v = v isens = 0.96 v vperi ?40 ma < i iasgx < ?0.5 ma iasg x cr 2x ?3% 14.9 +3% a 17.9 settling time (x = 1 to 5), r iasgx = 250 ? , no capacitive load at iasgx isense t isense 050sa 17.10 switch-on delay (x = 1 to 5) measured from rising edge of ssq to v iasgx = 0.1 v iasgx r iasgx = 250 ? , no capacitive load at iasgx iasg x t iasgx 050sa *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
61 4929b?auto?01/07 ata6264 [preliminary] 17.11 output voltage clamping (v isens v vperi ) i iasgx >cr y v vperi /r isen s (x = 1 to 5), (y = 1, 2) (v isens v vperi regulator active) isense v isense 0.96 v vperi 1.05 v vperi va 17.12 isens leakage current v isens = 0v to 0.96 v vperi isense i isense ?1.6 +1.6 a a 17.13 iasgx leakage current (x = 1 to 5) iasgx channel deactivated, 0v < v iasgx < v evz iasg x i iasgx ?1.6 +1.6 a a table 18-1. electrical characteristics (continued)? voltage/current sources (iasg x sources) no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
62 4929b?auto?01/07 ata6264 [preliminary] 19. amux (analog multiplexer for voltage measurements) various voltages and the chip temperature inside of the ata6264 can be measured at the ana- log measurement output uzp. different voltage dividers ensure that the values of the measured voltages at uzp are in the range of 0v to v peri . to select a specific measurement, a serial inter- face command has to be sent to the ata6264. for the list of measurable voltages and temperatures, refer to section 22. ?serial interface com- mands? on page 68 . the overall accuracy of the measurement part inside the ata6264 can be calculated using the following formula: figure 19-1. amux tolerances in order to describe the behavior of the whole measurement properly, the tolerance of the volt- age-divider ratio (ratio tolerance) and the offset tolerance of the uzp buffer (v uzpoffset ) are defined in separate points. the uzp buff er is defined in the following section. necessary for operation: v evz = 8v to 40v or v cp = 10v to 50v, v vint = 3.7v to 5.47v operating conditions of all other supply pins: v k30 , v vsat , v vperi and v vcore are within functional range limits, t j = ?40c to +150c other pins: as defined in section 4. ?functional range? on page 8 . v uzp v meas ratio ratio tolerance ------------------------------------------------------- - v uzpoffset = v uzp_max v in v uzp_offset v uzp_min vmeas typ. min. max. v uzp
63 4929b?auto?01/07 ata6264 [preliminary] table 19-1. electrical characteristics ? amux (analog multiplexer for voltage measurements) no. parameters test conditions pi n symbol min typ. max. unit type* 18.1 output offset error has to be calculated from the values of the differential measurement uzp v uzpoffset ?5 +15 mv a 18.2 ratio v k15 /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.05 4% 6.05 2.3% a a 18.2a ratio v k15 /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.12 6% 9.12 2.3% a a 18.3 ratio v k30 /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.04 6% 6.04 2.3% a a 18.3a ratio v k30 /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.11 6% 9.11 2.3% a a 18.4 ratio v evz /v uzp for v vperi = 5v uzp ratio 9.9 2.3% a 18.4a ratio v evz /v uzp for v vperi = 3.3v uzp ratio 14.78 2.6% a 18.5 ratio v sat /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.05 6% 6.05 2.3% a a 18.5a ratio v sat /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.12 6% 9.12 2.3% a a 18.6 ratio v vcore /v uzp for v vperi = v vcore = 5v uzp ratio 2 2.3% a 18.6a ratio v vcore /v uzp for v vperi > v vcore uzp ratio 0.995 1% a 18.7 ratio v isens /v uzp v vperi ?0.2v v isens 0.2v uzp ratio 0.992 1% a 18.8 ratio v k1 /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.06 3.5% 6.06 2.3% a a 18.8a ratio v k1 /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.16 3.5% 9.16 2.3% a a 18.9 ratio v k2 /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.06 3.5% 6.06 2.3% a a 18.9a ratio v k2 /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.16 3.5% 9.16 2.3% a a 18.10 ratio v iasg1 /v uzp for v vperi = 5v uzp ratio 10 3% a 18.10a ratio v iasg1 /v uzp for v vperi = 3.3v uzp ratio 14.75 3% a 18.11 ratio v iasg2 /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.04 6% 6.04 2.3% a a 18.11a ratio v iasg2 /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.11 6% 9.11 2.3% a a 18.12 ratio v iasg3 /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.04 6% 6.04 2.3% a a 18.12a ratio v iasg3 /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.11 6% 9.11 2.3% a a 18.13 ratio v iasg4 /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.04 6% 6.04 2.3% a a 18.13a ratio v iasg4 /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.11 6% 9.11 2.3% a a 18.14 ratio v iasg5 /v uzp uzp ratio 0.995 1% a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
64 4929b?auto?01/07 ata6264 [preliminary] 18.15 ratio v usp /v uzp for v vperi = 5v (1.5v to 3v) for v vperi = 5v (> 3v to 25v) uzp ratio 6.02 6% 6.02 2.3% a a 18.15a ratio v usp /v uzp for v vperi = 3.3v (1.5v to 3v) for v vperi = 3.3v (> 3v to 25v) uzp ratio 9.07 6% 9.07 2.3% a a special measurement (for det ection of band-gap defect) 18.16 ratio v vint /v uzp uzp ratio 3.99 2.6% a 18.17 voltage 0.9 v vperi switched to v uzp uzp ratio (0.9 v vperi ) 2% a 18.18 voltage 0.1 v vperi switched to v uzp uzp ratio (0.1 v vperi ) 2% a 18.19 input voltage range for proper function of 10 or 14.6 divider v input 640va 18.20 input voltage range for proper function of 6 or 9.1 divider v input 1.5 25 v a 18.21 input voltage range for proper function of 4 and 2 divider v input 46va 18.22 input voltage range for proper function of 1 buffer v input 0.2 v vperi ? 0.2 va 18.23 ratio v ref /v uzp ?2% 1 0% a table 19-1. electrical characteristics (continued)? amux (analog multiplexer for voltage measurements) no. parameters test conditions pi n symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
65 4929b?auto?01/07 ata6264 [preliminary] 20. uzp buffer the pin uzp is an analog output pin of the ata62 64. the uzp buffer is realized as a tristate out- put with the ability to drive to vperi as well as to gnda. the selected measurement result is given to the pin uzp as long as no new measurement is selected or the tristate command has been sent. driver capability is typically 4 ma. figure 20-1. functional principle of the uzp buffer necessary for operation: v peri > reset threshold, v cp = 10v to 50v, v vint = 3.7v to 5.47v operating conditions of all other supply pins: v k30 , v evz , v vsat and v vcore are within functional range limits, t j = ?40c to +150c other pins: as defined in section 4. ?functional range? on page 8 . driver circuitry tristate / normal operating voltage selected voltage from amux driver circuitry gnda 470 to 2000 ? 1 to 47 nf uzp 2 to 8 ma 2 to 8 ma v vperi
66 4929b?auto?01/07 ata6264 [preliminary] table 20-1. electrical characte ristics ? uzp buffer no. parameters test conditions pin symbol min typ. max. unit type* 19.1 output current high side, driving current with measurement activated v uzp = 0v, uzp connected to gnd uzp i uzp ?8 ?2 ma a 19.2 output current low side, sink current with measurement activated v uzp = v vperi uzp connected to gnd uzp i uzp 28maa 19.3 output settling time measured from rising edge of ssq to 90% of v uzp , no load at pin uzp uzp t uzp 10 s a 19.4 output settling time load 2 k ? /22 nf low-pass filter connected to pin uzp, measured from rising edge of ssq to 90% of v low pass filter out uzp t uzp 250 s a 19.5 output resistance uzp r uzp 100 ? a 19.6 linear measurement range uzp v uzp 0.2 v vperi ? 0.2 va 19.7 maximum output voltage v iasg5 switched via amux to uzp, v iasg5 = 6v uzp v uzp v vperi ? 50 mv v vperi + 50 mv va 19.8 output leakage current v uzp = 0v to v vperi , uzp buffer in tristate mode uzp i uzp ?5 +5 a a 19.9 output capacitance uzp buffer in tristate mode uzp c uzp 010pfd 19.10 time to switch to tristate mode measured from rising edge of ssq to i leak within tolerance uzp t uzp 3sa *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
67 4929b?auto?01/07 ata6264 [preliminary] 21. chip temperature measurement a serial interface command allows measuring a chip-temperature?dependent voltage which is generated by two diodes connected in series. three 2-diode sensors are connected in parallel and located in the following blocks: vperi, vcore, and vsat. the diodes are supplied by a temperature-constant current source, the voltage drop of the diodes is switched via amux to pin uzp. if the overtemperature level is exceeded, bit a7 in the status register is set to ?1?. necessary for operation: v int = 3.7v to 5.47v operating conditions of all other supply pins: v k30 , v evz , v vsat , v vperi and v vcore are within functional range limits, t j = ?40c to 150c other pins: as defined in section 4. ?functional range? on page 8 . table 21-1. electrical characteristics ? chip temperature measurement no. parameters test conditions pin symbol min typ. max. unit type* 20.1 temperature coefficient of chip-temperature sensor chip temperature switched via amux to uzp uzp v uzp ?4 ?3.6 ?3.2 mv/k d 20.2 output voltage temperature sensor chip temperature switched via amux to uzp, t j =25c uzp v uzp 1.29 1.54 v a 20.3 threshold overtemperature detection if overtemperature is detected, voltage drops by 35 mv uzp v uzp 155 185 c b 20.3a hysteresis for overtemperature detection uzp v uzp 525kb *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
68 4929b?auto?01/07 ata6264 [preliminary] 22. serial interface commands 22.1 overview all functions of the ata6264 are triggered by 16-bit serial interface commands. some of these commands are latched because their actions have to continue for a longer time. other com- mands have to be executed as long as no othe r command is received via the serial interface. the pin ssq (low active) is used to select the ata6264. if pin ssq is inactive (high), the output pin miso is disabled (tristate) and the signals at the pins sclk and mosi are ignored and do not affect the data in the serial interface register. with the falling edge at pin ssq , the ata6264 response on the previous command is latched in the ata6264 status register and, after a short delay time, the signal at pin miso is valid. with the rising edge at pin sclk, the data at pin mosi is shifted into the serial interface input register and the next bit of the status register is shifted to pin miso. a command received at pin mosi is valid and will be executed if the number of rising edges at pin sclk was exactly 16 during data transmission; otherwis e, the received si gnal will be ignored. the slave select pin, ssq, allows the individual selection of different slave spi devices. slave devices that are not selected do not interfere with spi bus activities. to ensure deactivation of the device in case of an open ssq pin, an internal current source is implemented to drive the ssq pin to high level (vperi). all commands, independent of their function, consist of 16 bits. the serial interface includes a 16-bit input shift register, 16-bit latches, and a decoder logic block for the generation of the spi command signals. to suppress data transfer errors in the case of spikes or glitches on the clock signal, a 16-clock-cycle counter is provided. only after 16 clock cycles does the rising edge of ssq cause an internal signal latch enable , which transfers the data from the shift register to the 16-bit latch. the data word is decoded to address the correct functional block. table 22-1. electrical characteristics ? serial interface commands no. parameters test conditions pin symbol min typ. max. unit type* 21.1 ssq to sclk rising-edge isolation sclk t iso 100 ns a (3) 21.2 ssq lag time ssq t lag 100 ns a (3) 21.3 fall time ssq, sclk, mosi t f 20 ns a (3) 21.3a fall time (2) miso t f 20 ns a 21.4 rise time ssq, sclk, mosi t r 20 ns a (3) 21.4a rise time (2) miso t r 20 ns a 21.5 data set-up time mosi t su 20 ns a (3) 21.6 data hold time mosi t hold 20 ns a (3) *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. voltage levels for serial interface timing measurements: high level = 0.7 v vperi , low level = 0.2 v vperi 2. timing specified with a 100-pf external load at pin miso 3. system requirement
69 4929b?auto?01/07 ata6264 [preliminary] 21.7 time from ssq falling edge to miso msb valid (2) miso t misomsb_v 0 400 ns a 21.8 time from sclk rising edge to miso valid (2) miso t misov 040nsa 21.9 time from ssq rising edge to miso tristate condition (2) miso t misohiz 040nsa 21.10 no-data time between serial interface commands t nodata 1.5 s a (3) 21.11 clock frequency clk f sclk 08mhza (3) 21.12 pull-up current vperi ssq r pu_ssq ?95 ?45 a a 21.13 pull-up current vperi sclk r pu_sclk ?95 ?45 a a 21.14 sclk high/low time sclk t cl 40 ns a (3) 21.15 input voltage high level ssq, sclk, mosi v h 0.5 v vperi a 21.16 input voltage low level ssq, sclk, mosi v l 0.25 v vperi a 21.17 input voltage hysteresis sclk v hys 50 250 mv a 21.18 output voltage high level i miso = ?1 ma to 0 ma miso v h v vperi ? 0.8 v vperi va 21.19 output voltage low level i miso = 0 ma to 1 ma miso v l 00.4va 21.20 output current high level driven to short circuit v vperi = 5v miso i miso ?47 ?10 ma a 21.21 output current low level sinking from vperi level v vperi = 5v miso i miso 645maa 21.22 input capacitance ssq, sclk, mosi c in 10 pf d 21.23 output capacitance s witched-off condition miso c miso 10 pf d 21.24 leakage current switched-off condition miso i miso ?10 +10 a a 21.25 number of clock cycles to be detected between falling and rising edge of ssq, to set error signal in status register to ?0? 16 16 a table 22-1. electrical characteristics (continued)? serial interface commands no. parameters test conditions pin symbol min typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. voltage levels for serial interface timing measurements: high level = 0.7 v vperi , low level = 0.2 v vperi 2. timing specified with a 100-pf external load at pin miso 3. system requirement
70 4929b?auto?01/07 ata6264 [preliminary] figure 22-1. timing serial interface 22.2 set commands after a reset due to the watchdog or undervoltage, all internal control registers and decoded sig- nals are set to their default values. serial interface commands other than those listed in table 22-2 on page 70 lead to an interrup- tion of measurements via amux, cause pin uzp to be switched to tristate, and iasg sources to be deactivated. the status of the latches does not change. 7. (< 400 ns) 5. (> 20 ns) 6. (> 20 ns) 4. (< 20 ns) not defined not defined not defined lsb msb #16 #1 lsb msb ssq sclk 3. (< 20 ns) 14. (> 40 ns) 8. (< 40 ns) 9. (< 40 ns) 1. (> 100 ns) 2. (> 100 ns) 10. (> 1.5 s) miso mosi table 22-2. set of serial interface commands command latch hex description msbyte lsbyte 7654321076543210 command option and data nop no 0000 0000000000000000 key latch yes 3xxx see table 22-3 on page 71 0011xxxxxxxxxxxx watchdog no 6xxx see table 22-4 on page 71 0110xxxxxxxxxxxx switch commands yes 9xxx see table 22-5 on page 71 1001xxxxxxxxxxxx initial programming n/a axxx see table 22-6 on page 72 1010xxxxxxxxxxxx diagnosis no cxxx see table 22-7 on page 72 1100xxxxxxxxxxxx iasg no fxxx see table 22-8 on page 73 1111xxxxxxxxxxxx test mode 1 no 55aa 0101010110101010 test mode 2 no aa55 1010101001010101 test mode 3 no 5500 0101010100000000 test-mode enable no 5a5a 0101101001011010
71 4929b?auto?01/07 ata6264 [preliminary] because the k1 and k2 interfaces are by default switched to iso (lin) mode, the commands 9cf0, 9cff, 9c00, and 9c0f default to invalid commands. table 22-3. key latch commands description msbyte lsbyte hex code 7654321076543210 key latch set 0011111111111111 3fff key latch reset (default) 0011000000000000 3000 table 22-4. watchdog commands description msbyte lsbyte hex code 7654321076543210 trigger watchdog 0110101001010101 6a55 configure prescaler 0110000011110abc 60fx table 22-5. switch commands description msbyte lsbyte hex code 7654321076543210 enable evz switching 1001101001011010 9a5a evz switched to 33v 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 930f evz switched to 23v (default) 1001001111110000 93f0 evz switched to external divider 1001001110010110 9396 cp-out switched to high-ohmic state (default) 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 960f cp-out switched to low-impedance state 1001011011110000 96f0 k1 interface works as iso9141 or lin interface (depending on iso/lin bit of initial programming) (default) 1001100111110000 99f0 k1 interface works in ls driver mode 1001100111111111 99ff k1 switched to high-ohmic state (default) 1001110011110000 9cf0 k1 switched to low-impedance state 1001110011111111 9cff k2 interface works as iso9141 interface (default) 1001100100000000 9900 k2 interface works in ls driver mode 1 0 0 1 1 0 0 1 0 0 0 0 1 1 1 1 990f k2 switched to high-ohmic state (default) 1001110000000000 9c00 k2 switched to low-impedance state 1001110000001111 9c0f
72 4929b?auto?01/07 ata6264 [preliminary] the initial programming command is only available in test mode. for more information about the programming flow and the register contents, see section 5.2 ?initial programming of the ata6264? on page 11 . table 22-6. initial programming (ip command) description msbyte lsbyte hex code 7654321076543210 write data to ip register 1 0 1 0 1 0 0 1 x x x x x x x x a9xx table 22-7. diagnosis commands description msbyte lsbyte hex code 7654321076543210 set uzp to tristate mode and switch off all measurements 1100000000000000 c000 switch v evz via amux to uzp 1100101000110001 ca31 switch v vsat via amux to uzp 1100101000110010 ca32 switch 90% v vperi via amux to uzp 1100101000110100 ca34 switch 10% v vperi via amux to uzp 1100101000111000 ca38 switch v vcore via amux to uzp 1100101001100001 ca61 switch v k15 via amux to uzp 1100101001100010 ca62 switch v k30 via amux to uzp 1100101001100100 ca64 switch v iref via amux to uzp 1100101001101000 ca68 switch v iasg1 via amux to uzp 1100101010010010 ca92 switch v iasg2 via amux to uzp 1100101010010100 ca94 switch v iasg3 via amux to uzp 1100101010011000 ca98 switch v iasg4 via amux to uzp 1100101011000001 cac1 switch v iasg5 via amux to uzp 1100101011000010 cac2 switch v usp via amux to uzp 1100101011000100 cac4 switch v k1 via amux to uzp 1100101011001000 cac8 switch v k2 via amux to uzp 1100101011100001 cae1 note: 1. uzp voltage will be influenced by the usp voltage
73 4929b?auto?01/07 ata6264 [preliminary] because the diagnosis commands are non-latchi ng commands, any new serial interface com- mands, except watchdog triggering (6a55) and the kx switching commands (9cxx), interrupt the diagnosis. note: a, b, and c represent the iasg number in binary format; only 001 = iasg1, 010 = iasg2, 011 = iasg3, 100 = iasg4, and 101 = iasg5 are valid commands because the iasg commands are non-latching commands, any new serial interface command, except watchdog triggering (6a55) and the kx switching commands (9cxx), interrupts the iasg function. switch v vint via amux to uzp 1100101011100010 cae2 switch voltage at chip-temperature sensor via amux to uzp 1100101011100100 cae4 (1) table 22-8. iasg commands description msbyte lsbyte hex code 7654321076543210 iasgx switched to 10v (mirror factor 10:1) 11110abc00110011 fx33 iasgx switched to 10v (mirror factor 15:1) 11110abc00111100 fx3c iasgx switched to 5v (mirror factor 10:1) 11110abc11000011 fxc3 iasgx switched to 5v (mirror factor15:1) 11110abc11001100 fxcc table 22-9. example description msbyte lsbyte hex code 7654321076543210 iasg1 switched to 10v (mirror factor 10:1) 1111000100110011 f133 iasg5 switched to 5v (mirror factor 15:1) 1111010111001100 f5cc table 22-7. diagnosis commands (continued) description msbyte lsbyte hex code 7654321076543210 note: 1. uzp voltage will be influenced by the usp voltage
74 4929b?auto?01/07 ata6264 [preliminary] 22.3 serial interface status register for all serial interface commands except the test-mode commands (55aah, aa55h, 5500h), the ata6264 status is available at the miso line. fo r the status register a 16-bit structure is used, one bit for each information. table 22-10. status register byte a byte b msbit lsbit msbit lsbit a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 table 22-11. information provided by the itemized bits of the status register bit set to information a7 high chip temperature reports overtemperature low chip temperature reports normal temperature a6 high overtemperature at k1 output low normal temperature at k1 output a5 high overtemperature at k2 output low normal temperature at k2 output a4 high latch for gkey function is set low latch for gkey function is not set a3 high evz switched to 33v, evz switched to external divider low evz switched to 23v a2 high cp-out switch is low impedance low cp-out switch is high ohmic a1 high cp-out voltage too low low cp-out voltage is in correct voltage range a0 high cp voltage too low low cp voltage is in correct voltage range b7 high voltage at pin usp above detection threshold low voltage at pin usp below detection threshold b6 high gnda or gndb disconnected low gnda and gndb connected b5 high previously sent serial interface command was invalid (default after power-on reset) low previously sent serial interface command was valid b4 high error during last serial interface transmission (default after power-on reset) low no error during last serial interface transmission b3 high ic is in test mode low ic is in normal mode b2 reflects bit b2 of the watchdog prescaler b1 reflects bit b1 of the watchdog prescaler b0 reflects bit b0 of the watchdog prescaler
75 4929b?auto?01/07 ata6264 [preliminary] the overtemperature bits a5, a6 and a7 are latched when overtemperature is detected. these bits will be reset with the next spi co mmand, unless overtemperature still exists. in the case of a reset, bits b4 and b5 are not set to their default state. these bits show the status before reset so that the microcontroller can de tect whether or not the ata6264 is in power-up state. table 22-12. test command issued via the miso line as a result of the test mode commands description command miso answer hex code test mode 1 55aa 1010101001010101 aa55 test mode 2 aa55 0101010110101010 55aa test mode 3 5500 0 0 0 0 0 0 0 1 a b c d e f g h 01xx note: a, b, c, d, e, f, g, h represent th e contents of the initial programming register
76 4929b?auto?01/07 ata6264 [preliminary] 23. test mode for better testability of the ata6264, a test mode is implemented. this mode is activated if the pins resq and txd1 are connected to gnd, the pins resq2 and txd2 are connected to vperi, and the serial interface command 5a5ah is sent to the ata6264. test mode is latched as long as the ata6264 is powered (v k30 > 4.2v to 5v and v k15 > 3v to 4v). in test mode the watchdog is disabled, which means that resq and resq2 depend on the voltage levels of the pins vcore, vperi and evz. in or der to provide the programming voltage at vsat for the ini- tial programming, v vsat is set to 11.7v (0.5v) in test mode if the lock bit is not set. after a reset, test mode is disabled (default). the following serial interface commands are used for the ata6264 supplier test: e6b5(h) and e6ba(h). figure 23-1. how to enable test mode v peri spi decoder enable testmode txd2 resq2 txd1 resq 5a5a (h) ssq miso mosi sclk
77 4929b?auto?01/07 ata6264 [preliminary] 24. application circuits figure 24-1. overview of a typical airbag system comsato svsat comevz fbevz vperifb vperi vsat comsati evz gndb ocevz gevz k30 k15 k15 k1 cp-out cp k2 resq2 uzp rxd2 iasg1 to 5 usp iref txd2 rxd1 resq gndd isens gnda txd1 comcoo serial interface sensor safety- system monitoring d, l, c net firing asic enable enable firing loops micro- controller comcoi vcore svcore k1 k30 k2 iasg1 to 5
78 4929b?auto?01/07 ata6264 [preliminary] figure 24-2. typical application circuit kl15 resq2 miso resq mosi kl30 k1 rxd1 txd1 rxd2 txd2 resq2 vint miso resq ssq sclk ssq sclk cp k30 usp mosi rxd1 txd1 rxd2 uzp uzp cp-out cp-out iref gndb gndd gnda k2 iasg3 iasg4 isens iasg5 iasg1 k1 txd2 gevz evz (33v) vperi (5v) vcore (5v) vsat (9v) evz fbevz comevz k15 comsato vperi vsat svcore vcore svsat svperi comcoo comcoi comsati ocevz iasg2 ata6264 k2 kl30
79 4929b?auto?01/07 ata6264 [preliminary] 26. package information 25. ordering information extended type number package remarks ata6264-altw p-tqfp44 tray ata6264-alqw p-tqfp44 taped and reeled specifications according to din technical drawings 10 0.05 12 0.2 8 12 22 44 34 33 0.2 23 1 11 0.8 issue: 1; 11.05.06 drawing-no.: 6.543-5131.01-4 0.1 0.05 0.6 0.15 1.4 0.05 dimensions in mm (acc. jedec outline no. mo-112) package: p-tqfp 44 0.37 -0.07 +0.08
80 4929b?auto?01/07 ata6264 [preliminary] 27. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4929b-auto-01/07 ? put datasheet in a new template ? section 23 ?test mode? on page 76 changed
81 4929b?auto?01/07 ata6264 [preliminary] 28. table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 1 1.1 block description .................................................................................................3 1.1.1 integrated boost converter evz .....................................................................3 1.1.2 integrated buck converter vsat ........ ................ ................ ................ ............3 1.1.3 integrated buck converter vcore ................................................................3 1.1.4 linear regulator vperi ... ................ ................ ............. ............. ............. ........3 1.1.5 blocks included ...............................................................................................3 2 pin configuration ..... ................ ................ ................. ................ ............... 4 3 absolute maximum ratings .... ................ ................. ................ ............... 6 4 functional range ......... ................. ................ ................. .............. ............ 8 4.1 protection against substrate currents .................................................................9 5 supply currents ......... ................ ................. ................ ................. .......... 10 5.1 discharger circuit ...............................................................................................11 5.2 initial programming of the ata6264 ..................................................................11 5.3 start-up and power-down procedure .................................................................14 5.3.1 start-up procedure if vvcore is programmed to be 5v or 2.5v ................15 5.3.2 the power-down procedure takes place in different phases .....................15 5.3.3 start-up procedure if vvcore programmed to be 1.88v ...........................16 5.3.4 the power-down procedure for vvcore is programmed to be 1.88v .......17 6 power supply sequencing ...... ................ ................. ................ ............. 18 7 charge pump ............ ................ ................ ................. ................ ............. 20 8 gkey function ............. ................. ................ ................. .............. .......... 22 9 evz step-up regulator ....... .............. ............... .............. .............. .......... 24 10 vsat power supply ............ .............. ............... .............. .............. .......... 30 11 vperi power supply .......... .............. ............... .............. .............. .......... 33 12 vcore power supply ........ .............. ............... .............. .............. .......... 35 13 usp comparator for general purpose ... ................. ................ ............. 39 14 reference voltage and reference current generation ....... ............... 40 15 reset function (pin resq and pin resq2) ................ .............. .......... 41 16 watchdog function ................. ................ ................. ................ ............. 47
82 4929b?auto?01/07 ata6264 [preliminary] 17 lin/iso 9141 interfaces ......... .............. .............. .............. .............. ........ 54 18 voltage/current sources (i asgx sources) ................. .............. .......... 58 19 amux (analog multiplexer for voltage measurements) .... ................. 62 20 uzp buffer ............. .............. .............. ............... .............. .............. .......... 65 21 chip temperature measurement .................... .............. .............. .......... 67 22 serial interface commands ..... ................ ................. ................ ............. 68 22.1 overview ............................................................................................................68 22.2 set commands ..................................................................................................70 22.3 serial interface status register .........................................................................74 23 test mode ............ ................ .............. ............... .............. .............. .......... 76 24 application circuits ........ ................ ................. .............. .............. .......... 77 25 ordering information .......... .............. ............... .............. .............. .......... 79 26 package information .......... .............. ............... .............. .............. .......... 79 27 revision history ....... ................ ................ ................. ................ ............. 80
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